Patents by Inventor Yasuo Nakamura

Yasuo Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10411366
    Abstract: A connector (A) includes a barrel (23) formed in a terminal fitting (15) and crimped to surround a front end part of a coated wire (11). The barrel (23) has a base plate (24) connected to a bottom portion (22) of a terminal body (16) and two crimping pieces (27) extending from both widthwise sides of the base plate (24). A molded portion (30) surrounds the barrel (23) over an entire periphery and is configured to cover the front end part of the coated wire (11) in a liquid-tight manner. A housing (35) is formed with a terminal accommodation chamber (36) for accommodating the entire terminal fitting (15). The base plate (24) is raised with respect to the bottom portion (22) of the terminal body (16).
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: September 10, 2019
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Shunya Takeuchi, Yasuo Omori, Hajime Matsui, Takehiro Nakata, Yoshiaki Yamano, Tetsuya Nakamura
  • Publication number: 20190266017
    Abstract: A parallel process apparatus connecting electronic controllers via buses includes: a process request acceptance section that accepts process requests to the electronic controllers; and a process execution section that, while multiple process requests are simultaneously accepted, arbitrates the multiple process requests being accepted, and parallelizes multiple processes in accordance with the multiple process requests.
    Type: Application
    Filed: May 9, 2019
    Publication date: August 29, 2019
    Inventors: Sho NAKAMURA, Yuzo HARATA, Kazuaki HAYAKAWA, Tatsuya SATO, Yasuo MORITA
  • Publication number: 20190238024
    Abstract: A motor includes a rotating shaft, a rotor, a stator, a bracket, and a control device mounted on the bracket. The bracket includes a cylindrical bracket main body, and a stator frame which faces the bracket main body across a clearance and holds an outer surface of the stator on the radially inward side of the bracket main body. The control device is mounted on the bracket main body. The bracket is provided with a cooling passage, and an inflow port and an outflow port connected with the cooling passage. The cooling passage includes a control device cooling passage provided between the bracket main body and the control device, a stator cooling passage provided between the bracket main body and the stator frame, and a communication passage coupling the control device cooling passage and the stator cooling passage.
    Type: Application
    Filed: April 12, 2019
    Publication date: August 1, 2019
    Inventors: Masato NAKANISHI, Yasuo ISHIYAMA, Yoshinobu NAKAMURA, Takumi OKADA
  • Patent number: 10305345
    Abstract: A motor includes a rotating shaft, a rotor, a stator, a bracket, and a control device mounted on the bracket. The bracket includes a cylindrical bracket main body, and a stator frame which faces the bracket main body across a clearance and holds an outer surface of the stator on the radially inward side of the bracket main body. The control device is mounted on the bracket main body. The bracket is provided with a cooling passage, and an inflow port and an outflow port connected with the cooling passage. The cooling passage includes a control device cooling passage provided between the bracket main body and the control device, a stator cooling passage provided between the bracket main body and the stator frame, and a communication passage coupling the control device cooling passage and the stator cooling passage.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: May 28, 2019
    Assignee: NIDEC CORPORATION
    Inventors: Masato Nakanishi, Yasuo Ishiyama, Yoshinobu Nakamura, Takumi Okada
  • Publication number: 20190148473
    Abstract: The present invention provides a light-emitting device comprising a first light-emitting element that emits red light, a second light-emitting element that emits green light, a third light-emitting element that emits blue light, and a color filter, where the color filter comprises a first coloring layer that selectively transmits red light, a second coloring layer that selectively transmits green light, and a third coloring layer that selectively transmits blue light, the first to third light-emitting elements respectively correspond to the first to third coloring layers, wherein each of the first to third light-emitting elements has a first electrode, an electroluminescent layer on the first electrode, and a second electrode on the electroluminescent layer, and wherein the electroluminescent layer includes a layer in contact with the second electrode, and a metal oxide or a benzoxazole derivative is included in the layer in contact with the second electrode.
    Type: Application
    Filed: December 18, 2018
    Publication date: May 16, 2019
    Inventors: Shunpei YAMAZAKI, Junichiro SAKATA, Hisao IKEDA, Yasuo NAKAMURA, Keiko SAITO
  • Patent number: 10286859
    Abstract: A wire harness waterproofing structure includes a grommet that includes a pipe-formed body part the periphery of which is watertightly attached to a through hole which is bored in a body panel which separates a compartment outside part and a compartment inside part, and a small diameter tubular part one end of which is connected to the pipe-formed body part, a wire harness that includes a plurality of electric wires inserted through the tubular part in an unbound state and is wired with a predetermined height difference relative to the through hole, a diameter-increased part that are provided on at least one of the electric wires to forms a gap between the electric wires adjacent to the one of the electric wires.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: May 14, 2019
    Assignee: YAZAKI CORPORATION
    Inventors: Yasuo Iimori, Yasuhiro Mochizuki, Yoshinori Nakamura, Kei Nunome
  • Patent number: 10290742
    Abstract: It is an object to provide a semiconductor device typified by a display device having a favorable display quality, in which parasitic resistance generated in a connection portion between a semiconductor layer and an electrode is suppressed and an adverse effect such as voltage drop, a defect in signal wiring to a pixel, a defect in grayscale, and the like due to wiring resistance are prevented. In order to achieve the above object, a semiconductor device according to the present invention may have a structure where a wiring with low resistance is connected to a thin film transistor in which a source electrode and a drain electrode that include metal with high oxygen affinity are connected to an oxide semiconductor layer with a suppressed impurity concentration. In addition, the thin film transistor including the oxide semiconductor may be surrounded by insulating films to be sealed.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: May 14, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Masahiro Takahashi, Hideyuki Kishida, Akiharu Miyanaga, Yasuo Nakamura, Junpei Sugao, Hideki Uochi
  • Patent number: 10205030
    Abstract: To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: February 12, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Kengo Akimoto, Yasuo Nakamura
  • Patent number: 10192946
    Abstract: The present invention provides a light-emitting device comprising a first light-emitting element that emits red light, a second light-emitting element that emits green light, a third light-emitting element that emits blue light, and a color filter, where the color filter comprises a first coloring layer that selectively transmits red light, a second coloring layer that selectively transmits green light, and a third coloring layer that selectively transmits blue light, the first to third light-emitting elements respectively correspond to the first to third coloring layers, wherein each of the first to third light-emitting elements has a first electrode, an electroluminescent layer on the first electrode, and a second electrode on the electroluminescent layer, and wherein the electroluminescent layer includes a layer in contact with the second electrode, and a metal oxide or a benzoxazole derivative is included in the layer in contact with the second electrode.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: January 29, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Hisao Ikeda, Yasuo Nakamura, Keiko Saito
  • Publication number: 20180350998
    Abstract: By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased.
    Type: Application
    Filed: August 2, 2018
    Publication date: December 6, 2018
    Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Masahiro TAKAHASHI, Hideyuki KISHIDA, Akiharu MIYANAGA, Junpei SUGAO, Hideki UOCHI, Yasuo NAKAMURA
  • Patent number: 10043915
    Abstract: By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: August 7, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Masahiro Takahashi, Hideyuki Kishida, Akiharu Miyanaga, Junpei Sugao, Hideki Uochi, Yasuo Nakamura
  • Publication number: 20180212189
    Abstract: A light emitting device having a structure in which oxygen and moisture are prevented from reaching light emitting elements, and a method of manufacturing the same, are provided. Further, the light emitting elements are sealed by using a small number of process steps, without enclosing a drying agent. The present invention has a top surface emission structure. A substrate on which the light emitting elements are formed is bonded to a transparent sealing substrate. The structure is one in which a transparent second sealing material covers the entire surface of a pixel region when bonding the two substrates, and a first sealing material (having a higher viscosity than the second sealing material), which contains a gap material (filler, fine particles, or the like) for protecting a gap between the two substrates, surrounds the pixel region. The two substrates are sealed by the first sealing material and the second sealing material.
    Type: Application
    Filed: March 23, 2018
    Publication date: July 26, 2018
    Inventors: Takeshi Nishi, Yasuo Nakamura
  • Patent number: 9936931
    Abstract: In image data obtained, the radius and the ulna, and interosseous soft tissue between two bones are identified. A midpoint (Ygk) of the length of the interosseous soft tissue in a Y axis direction in (Xk) coordinates is determined. This midpoint is determined in multiple coordinates, and an approximate straight line of these midpoints is determined and set as a reference line. The foot of the perpendicular from the ulna styloid process to the reference line is set as a reference position. A region of interest is set in a position at a predetermined distance from the reference position along the reference line.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: April 10, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Ryutaro Adachi, Yasuo Nakamura, Naoto Kato
  • Patent number: 9929377
    Abstract: A light emitting device having a structure in which oxygen and moisture are prevented from reaching light emitting elements, and a method of manufacturing the same, are provided. Further, the light emitting elements are sealed by using a small number of process steps, without enclosing a drying agent. The present invention has a top surface emission structure. A substrate on which the light emitting elements are formed is bonded to a transparent sealing substrate. The structure is one in which a transparent second sealing material covers the entire surface of a pixel region when bonding the two substrates, and a first sealing material (having a higher viscosity than the second sealing material), which contains a gap material (filler, fine particles, or the like) for protecting a gap between the two substrates, surrounds the pixel region. The two substrates are sealed by the first sealing material and the second sealing material.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: March 27, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Nishi, Yasuo Nakamura
  • Publication number: 20180047852
    Abstract: It is an object to provide a semiconductor device typified by a display device having a favorable display quality, in which parasitic resistance generated in a connection portion between a semiconductor layer and an electrode is suppressed and an adverse effect such as voltage drop, a defect in signal wiring to a pixel, a defect in grayscale, and the like due to wiring resistance are prevented. In order to achieve the above object, a semiconductor device according to the present invention may have a structure where a wiring with low resistance is connected to a thin film transistor in which a source electrode and a drain electrode that include metal with high oxygen affinity are connected to an oxide semiconductor layer with a suppressed impurity concentration. In addition, the thin film transistor including the oxide semiconductor may be surrounded by insulating films to be sealed.
    Type: Application
    Filed: October 10, 2017
    Publication date: February 15, 2018
    Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Masahiro TAKAHASHI, Hideyuki KISHIDA, Akiharu MIYANAGA, Yasuo NAKAMURA, Junpei SUGAO, Hideki UOCHI
  • Publication number: 20180040741
    Abstract: To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.
    Type: Application
    Filed: October 3, 2017
    Publication date: February 8, 2018
    Inventors: Hidekazu MIYAIRI, Kengo AKIMOTO, Yasuo NAKAMURA
  • Patent number: 9865742
    Abstract: It is an object to provide a semiconductor device typified by a display device having a favorable display quality, in which parasitic resistance generated in a connection portion between a semiconductor layer and an electrode is suppressed and an adverse effect such as voltage drop, a defect in signal wiring to a pixel, a defect in grayscale, and the like due to wiring resistance are prevented. In order to achieve the above object, a semiconductor device according to the present invention may have a structure where a wiring with low resistance is connected to a thin film transistor in which a source electrode and a drain electrode that include metal with high oxygen affinity are connected to an oxide semiconductor layer with a suppressed impurity concentration. In addition, the thin film transistor including the oxide semiconductor may be surrounded by insulating films to be sealed.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: January 9, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Masahiro Takahashi, Hideyuki Kishida, Akiharu Miyanaga, Yasuo Nakamura, Junpei Sugao, Hideki Uochi
  • Patent number: 9793416
    Abstract: To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: October 17, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Kengo Akimoto, Yasuo Nakamura
  • Patent number: 9767748
    Abstract: An object is to provide a convenient display device which consumes sufficiently small amount of power and a method for driving such a display device. The display device can be in an off state with a still image displayed in a still image display mode in which a pixel electrode and a common electrode which are for applying a voltage to the display element are brought into a floating state so that a voltage applied to the display element is held, and a still image is displayed without further supply of a potential. The display device is put to an off state with a desired image displayed in the still image display mode, whereby the display device can have a higher level of security and can be more convenient.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: September 19, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kenichi Wakimoto, Yasuo Nakamura
  • Patent number: 9735209
    Abstract: An object is to provide a light-emitting module in which a light-emitting element suffering a short-circuit failure does not cause wasteful electric power consumption. Another object is to provide a light-emitting panel in which a light-emitting element suffering a short-circuit failure does not allow the reliability of an adjacent light-emitting element to lower. Focusing on heat generated by a light-emitting element suffering a short-circuit failure, provided is a structure in which electric power is supplied to a light-emitting element through a positive temperature coefficient thermistor (PTC thermistor) thermally coupled with the light-emitting element.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: August 15, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masaaki Hiroki, Satoshi Seo, Yasuo Nakamura