Patents by Inventor Yasushi Fujinami

Yasushi Fujinami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10338984
    Abstract: Detecting a defective cell in a memory in consideration of an error property difference depending on the storage state. A determination unit determines whether there is a possibility of defect for each of unit-of-storages on a memory cell formed with a non-volatile memory. The non-volatile memory undergoes either a reset operation that transitions a state from a low resistive state (LRS) to a high resistive state (HRS) or a set operation that transitions the state from the high resistive state to the low resistive state. The determination unit determines a unit-of-storage in which the number of errors in predetermined one of the reset operation and the set operation has exceeded a predetermined standard, as a unit-of-storage suspected of having a defect.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: July 2, 2019
    Assignee: SONY CORPORATION
    Inventors: Yasushi Fujinami, Kenichi Nakanishi, Tsunenori Shiimoto, Tetsuya Yamamoto, Tatsuo Shinbashi, Hideaki Okubo, Haruhiko Terada, Ken Ishii, Hiroyuki Iwaki, Matatoshi Honjo
  • Patent number: 10310742
    Abstract: The write reliability of a nonvolatile memory is improved by performing accurate verification of write data. In a memory controller of an information processing system, a determination unit determines whether a state of a memory cell after writing data is stable in a nonvolatile memory including the memory cell having an unstable state period after writing data. A verification unit performs verification by comparing read data which is read from the memory cell where the data is written on the basis of a result of the determination, with write data involved in the writing. A write control unit performs writing of the data and rewriting of the write data based on a result of the verification.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: June 4, 2019
    Assignee: Sony Corporation
    Inventor: Yasushi Fujinami
  • Publication number: 20190056884
    Abstract: The write time is to be shortened in a storage device using memories that require different write times from each other, such as nonvolatile memories. In a memory controller including a plurality of write request holding units and a selection unit, the write request holding units holds a write request with respect to each of a plurality of memory modules that require different write times from one another. The selection unit selects one of the plurality of write request holding units in accordance with memory state information indicating whether each of the plurality of memory modules is in a busy state, and causes outputting of the write request.
    Type: Application
    Filed: July 27, 2016
    Publication date: February 21, 2019
    Inventors: KEN ISHII, HIROYUKI IWAKI, KENICHI NAKANISHI, YASUSHI FUJINAMI, TATSUO SHINBASHI
  • Patent number: 10120614
    Abstract: A storage device writes data at a high speed. The storage device is provided with a data area and a control unit. In the data area, a write position is specified by a write address. Also, the control unit writes the data in the write address when instructed to write the data in the write address, and generates an address different from the write address in which the writing is performed as an alternative write address and writes the data in the alternative write address when the writing of the data is unsuccessful.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: November 6, 2018
    Assignee: SONY CORPORATION
    Inventors: Hiroyuki Iwaki, Ken Ishii, Ryoji Ikegaya, Kenichi Nakanishi, Yasushi Fujinami, Naohiro Adachi
  • Publication number: 20180232178
    Abstract: An access speed when a memory controller accesses a memory is improved. Each time any one of two different types of commands is input, a holding unit holds the input command. A priority mode switching unit switches a priority command which should have priority out of the two commands from one of the two commands to the other. A command processing unit preferentially extracts priority commands sequentially from the holding unit, and then sequentially extracts commands which are not the priority commands from the holding unit.
    Type: Application
    Filed: June 15, 2016
    Publication date: August 16, 2018
    Inventors: Hiroyuki Iwaki, Ken Ishii, Yasushi Fujinami, Kennichi Nakanishi, Tatsuo Shinbashi
  • Publication number: 20180143871
    Abstract: A data holding characteristic of a memory cell is improved in a memory system in which data is encoded and written to a memory cell. A first candidate parity generation unit generates, as a first candidate parity, a parity for detecting an error in an information section in which a predetermined value is assigned in a predetermined variable area. A second candidate parity generation unit generates, as a second candidate parity, a parity for detecting an error in the information section in which a value different from the predetermined value is assigned in the predetermined variable area. A selection unit selects a parity that satisfies a predetermined condition from among the first and second candidate parities as a selection parity. An output unit outputs a codeword constituted by the information section corresponding to the selection parity and the selection parity.
    Type: Application
    Filed: April 15, 2016
    Publication date: May 24, 2018
    Inventors: Tatsuo Shinbashi, Kenichi Nakanishi, Yasushi Fujinami, Hiroyuki Iwaki, Ken Ishii, Hideaki Okubo
  • Patent number: 9852812
    Abstract: There is provided a storage apparatus that includes an address obtaining section, and a write processing section. The address obtaining section is configured to obtain a normal write address and an alternative write address before data writing to the normal write address, the normal write address being designated as a destination of the data writing, the alternative write address being used when the data writing is failed. The write processing section is configured to perform the data writing to the normal write address when instructed for the data writing, and perform the data writing to the alternative write address when the data writing to the normal write address is failed.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: December 26, 2017
    Assignee: Sony Corporation
    Inventors: Hiroyuki Iwaki, Ken Ishii, Ryoji Ikegaya, Kenichi Nakanishi, Yasushi Fujinami, Naohiro Adachi
  • Publication number: 20170357572
    Abstract: To secure flexibility of the memory extension area which is secured on the memory of the host computer and used by the memory controller. [Solution] A controller memory stores data corresponding to an area allocated to a memory in a memory controller configured to control the memory. An access control unit allocates a partial area of the controller memory to a host memory in a host computer and uses the areas as a memory extension area. The extension area managing unit performs management so that a size of the memory extension area in the host memory is changeable.
    Type: Application
    Filed: October 8, 2015
    Publication date: December 14, 2017
    Applicant: Sony Corporation
    Inventors: Hideaki Okubo, Kenichi Nakanishi, Yasushi Fujinami
  • Patent number: 9836392
    Abstract: A storage control apparatus includes: a pre-processing-execution determining block for determining whether or not either one of an erase operation and a program operation is to be executed as pre-processing in a write operation to be carried out on a predetermined data area to serve as a write-operation object; and a pre-read processing block for reading out pre-read data from the data area prior to the write operation if a result of the determination indicates that the pre-processing is to be executed. The apparatus further includes a bit operating block for carrying out: the pre-processing and one of the erase and program operations which is not the pre-processing as post-processing if a result of the determination indicates that the pre-processing is to be executed; and the post-processing without carrying out the pre-processing if a determination result indicates that the pre-processing is not to be executed.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: December 5, 2017
    Assignee: SONY CORPORATION
    Inventors: Naohiro Adachi, Keiichi Tsutsui, Kenichi Nakanishi, Hideaki Okubo, Yasushi Fujinami, Ken Ishii
  • Publication number: 20170322842
    Abstract: Reduction in deterioration of a memory cell in a non-volatile memory is achieved. A memory controller is configured to include a time measuring unit, an elapsed time determination unit, and a read unit. The time measuring unit measures time elapsed from predetermined timing on an address where data written. The elapsed time determination unit determines whether the elapsed time exceeds a fixed amount of time upon receiving an instruction to read out the data from the address. The read control unit causes reading-out of the data from the address to pause in a case where the elapsed time is determined not to exceed the fixed amount of time.
    Type: Application
    Filed: October 8, 2015
    Publication date: November 9, 2017
    Inventors: HIROYUKI IWAKI, KEIICHI TSUTSUI, LUI SAKAI, KENICHI NAKANISHI, HIDEAKI OKUBO, YASUSHI FUJINAMI
  • Patent number: 9792173
    Abstract: Disclosed is an interface control circuit including an error detection unit, an error correction unit, and an adjustment control unit. The error detection unit is configured to detect whether an error occurs in error correction coded data transmitted via an interface. The error correction unit is configured to execute error correction processing of correcting the error when the error occurs. The adjustment control unit is configured to start adjustment processing of adjusting a transmission characteristic of the interface when the error occurs.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: October 17, 2017
    Assignee: Sony Corporation
    Inventors: Naohiro Adachi, Yoshiyuki Shibahara, Yasushi Fujinami
  • Publication number: 20170293513
    Abstract: [Object] To sufficiently reduce frequency of error occurrence in memory cells. [Solution] A reading unit reads read data from a memory cell, the read data including an information bit and reversal information for determining whether or not the information bit has been reversed. In addition, an error detection/correction unit detects the presence or absence of an error in the information bit and corrects the error. A data reversing unit reverses the information bit that has the error corrected and the reversal information. Furthermore, a writing unit writes the reversed information bit and the reversed reversal information in the memory cell.
    Type: Application
    Filed: July 22, 2015
    Publication date: October 12, 2017
    Inventors: Tatsuo Shinbashi, Keiichi Tsutsui, Hideaki Okubo, Lui Sakai, Kenichi Nakanishi, Yasushi Fujinami
  • Publication number: 20170277442
    Abstract: The write reliability of a nonvolatile memory is improved by performing accurate verification of write data. In a memory controller of an information processing system, a determination unit determines whether a state of a memory cell after writing data is stable in a nonvolatile memory including the memory cell having an unstable state period after writing data. A verification unit performs verification by comparing read data which is read from the memory cell where the data is written on the basis of a result of the determination, with write data involved in the writing. A write control unit performs writing of the data and rewriting of the write data based on a result of the verification.
    Type: Application
    Filed: July 14, 2015
    Publication date: September 28, 2017
    Inventor: Yasushi Fujinami
  • Publication number: 20170255502
    Abstract: Detecting a defective cell in a memory in consideration of an error property difference depending on the storage state. A determination unit determines whether there is a possibility of defect for each of unit-of-storages on a memory cell formed with a non-volatile memory. The non-volatile memory undergoes either a reset operation that transitions a state from a low resistive state (LRS) to a high resistive state (HRS) or a set operation that transitions the state from the high resistive state to the low resistive state. The determination unit determines a unit-of-storage in which the number of errors in predetermined one of the reset operation and the set operation has exceeded a predetermined standard, as a unit-of-storage suspected of having a defect.
    Type: Application
    Filed: July 9, 2015
    Publication date: September 7, 2017
    Inventors: YASUSHI FUJINAMI, KENICHI NAKANISHI, TSUNENORI SHIIMOTO, TETSUYA YAMAMOTO, TATSUO SHINBASHI, HIDEAKI OKUBO, HARUHIKO TERADA, KEN ISHII, HIROYUKI IWAKI, MATATOSHI HONJO
  • Publication number: 20170185478
    Abstract: The convenience of an information processing system is improved. In a memory controller of the information processing system, a request generation unit generates, with respect to a nonvolatile memory including a data area in which data is stored and a redundancy area in which a redundancy for performing error detection and error correction of the data is stored, a request of requesting writing or reading for any one of the data, and the redundancy, a code word constituted of the data and the redundancy. A control unit issues the generated request and controls writing and reading with respect to the nonvolatile memory.
    Type: Application
    Filed: June 23, 2015
    Publication date: June 29, 2017
    Applicant: SONY CORPORATION
    Inventors: LUI SAKAI, KEIICHI TSUTSUI, YASUSHI FUJINAMI, HIROYUKI IWAKI, KEN ISHII, NAOHIRO ADACHI, RYOJI IKEGAYA, KENICHI NAKANISHI
  • Publication number: 20170109099
    Abstract: A storage device writes data at a high speed. The storage device is provided with a data area and a control unit. In the data area, a write position is specified by a write address. Also, the control unit writes the data in the write address when instructed to write the data in the write address, and generates an address different from the write address in which the writing is performed as an alternative write address and writes the data in the alternative write address when the writing of the data is unsuccessful.
    Type: Application
    Filed: May 19, 2015
    Publication date: April 20, 2017
    Inventors: HIROYUKI IWAKI, KEN ISHII, RYOJI IKEGAYA, KENICHI NAKANISHI, YASUSHI FUJINAMI, NAOHIRO ADACHI
  • Patent number: 9608668
    Abstract: Provided is an error correcting method including: executing, by an error-position detector, a determination process if a received word fails to satisfy a predetermined condition, the received word having a plurality of symbols, the determination process including determining if a determination-target symbol has an error or not, and detecting an error position, the error position being a position of the symbol having an error; changing, by a determination-target changing unit, the position of the determination-target symbol of the received word every time the determination process is executed; detecting, by an undetected-position detector, if the predetermined condition is satisfied, the error position of the symbol, for which the determination process is not executed, based on a relation between the error position and a variable generated from the received word; and correcting, by an error corrector, an error at the error position detected by the error-position detector and the undetected-position detector.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: March 28, 2017
    Assignee: Sony Corporation
    Inventors: Ryoji Ikegaya, Tatsuo Shinbashi, Yasushi Fujinami
  • Patent number: 9542270
    Abstract: An error detection-correction unit reads system information for operating a system from a first memory and performs error detection-correction processing. A control unit supplies the system information to a host computer in a case where the error detection-correction processing is successful. In addition, the control unit reads a backup of the system information from a second memory that is different from the first memory and supplies the backup of the system information to the host computer in a case where the detection-correction processing fails.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: January 10, 2017
    Assignee: Sony Corporation
    Inventors: Lui Sakai, Keiichi Tsutsui, Yasushi Fujinami
  • Patent number: 9455017
    Abstract: A storage control device includes: a partial unit buffer configured to hold at least one data assigned to a partial unit, in which the partial unit is one of a plurality of partial units that are each a division of a write unit for a memory; and a request generation section configured to generate, upon indication of a busy state in the memory for any of the partial units, a write request for the write unit of the memory when the holding of the data assigned to that partial unit is possible in the partial unit buffer.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: September 27, 2016
    Assignee: Sony Corporation
    Inventors: Kenichi Nakanishi, Yasushi Fujinami, Ken Ishii, Hiroyuki Iwaki, Kentarou Mori
  • Patent number: 9449684
    Abstract: Provided is a storage control device including: a detection unit which detects a first timing for performing a first rewriting process of performing only a first operation from among the first operation and a second operation, in a memory cell array in which each bit transitions to a first storage state by the first operation and transitions to a second storage state by the second operation; and a request unit which makes a request for the first rewriting process with respect to the memory cell array, when the first timing is detected.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: September 20, 2016
    Assignee: Sony Corporation
    Inventors: Hideaki Okubo, Kenichi Nakanishi, Yasushi Fujinami, Lui Sakai