Patents by Inventor Yasushi Fujinami

Yasushi Fujinami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220276837
    Abstract: In one example, an arithmetic apparatus includes arithmetic circuits, a signal output circuit, and a common wiring unit. The common wiring unit electrically connects signal output lines of the signal output circuit to input lines included with each of the arithmetic circuit units. The arithmetic circuits include a first arithmetic circuit and a second arithmetic circuit. The electrical signals output from the signal output lines are input into the as electrical signals corresponding to the input values via the common wiring unit. The extending directions of the output lines of the first arithmetic circuit and the output lines of the second arithmetic circuit unit are parallel to each other.
    Type: Application
    Filed: August 13, 2020
    Publication date: September 1, 2022
    Inventor: Yasushi Fujinami
  • Publication number: 20220236952
    Abstract: An arithmetic apparatus includes first and second arithmetic circuit units. Multiply-accumulate signals output from a plurality of output lines of the first arithmetic circuit unit or signals generated on the basis of the multiply-accumulate signals are input into a plurality of input lines of the second arithmetic circuit unit. An extending direction of the plurality of input lines of the first arithmetic circuit unit and an extending direction of the plurality of output lines of the second arithmetic circuit unit are parallel to each other.
    Type: Application
    Filed: May 15, 2020
    Publication date: July 28, 2022
    Inventor: YASUSHI FUJINAMI
  • Patent number: 11262936
    Abstract: The write time is to be shortened in a storage device using memories that require different write times from each other, such as nonvolatile memories. In a memory controller including a plurality of write request holding units and a selection unit, the write request holding units holds a write request with respect to each of a plurality of memory modules that require different write times from one another. The selection unit selects one of the plurality of write request holding units in accordance with memory state information indicating whether each of the plurality of memory modules is in a busy state, and causes outputting of the write request.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: March 1, 2022
    Assignee: SONY CORPORATION
    Inventors: Ken Ishii, Hiroyuki Iwaki, Kenichi Nakanishi, Yasushi Fujinami, Tatsuo Shinbashi
  • Publication number: 20210376836
    Abstract: A signal processing circuit (12) outputs, in a case where a first timing at which a first input signal changes is earlier than or same as a second timing at which a second input signal changes, a first output signal at the first timing and a second output signal at the second timing, and outputs, in a case where the first timing is later than the second timing, the first output signal and the second output signal at the second timing.
    Type: Application
    Filed: July 5, 2019
    Publication date: December 2, 2021
    Inventors: AKITO SEKIYA, TOMOHIRO MATSUMOTO, HIROYUKI YAMAGISHI, YASUSHI FUJINAMI, YUSUKE OIKE, RYOJI IKEGAYA
  • Publication number: 20210318853
    Abstract: An arithmetic logic unit according to an embodiment of the present technology includes: a plurality of input lines; and a multiply-accumulate operation device. Pulse signals corresponding to input values are input to the plurality of input lines. The multiply-accumulate operation device includes a plurality of multiplication units that generates, on the basis of the pulse signals input to each of the plurality of input lines, charges corresponding to multiplication values obtained by multiplying the input values by weight values, and an output unit that outputs a multiply-accumulate signal representing a sum of the multiplication values by accumulating the charges corresponding to the multiplication values generated by each of the plurality of multiplication units. A value of at least one of the input value or the weight value is limited.
    Type: Application
    Filed: July 12, 2019
    Publication date: October 14, 2021
    Inventors: Takashi Morie, Ha karu Tamukoh, Quan Wang, Yasushi Fujinami
  • Publication number: 20210240944
    Abstract: A multiply-accumulate device (10) includes: a comparison unit (18) that compares, with a threshold voltage, a voltage generated by an electric charge stored in a storage unit (14), and outputs an output signal at timing at which the voltage exceeds the threshold voltage; and a control circuit (110) that reduces, based on a predetermined set value, a charging current to the storage unit (14) from a plurality of input units (13) connected to the storage unit (14).
    Type: Application
    Filed: July 5, 2019
    Publication date: August 5, 2021
    Inventors: Yasushi Fujinami, Hiroyuki Yamagishi
  • Publication number: 20210191691
    Abstract: A multiply-accumulate system (1) includes: a statistic calculation unit (111) that executes a standardization calculation for an input signal; and a multiply-accumulate device (10) that executes multiplication-accumulation based on the standardized input signal.
    Type: Application
    Filed: July 4, 2019
    Publication date: June 24, 2021
    Inventors: Yasushi Fujinami, Hiroyuki Yamagishi
  • Patent number: 11029881
    Abstract: The order of read access to a memory is appropriately determined. A memory system includes a plurality of memories and a memory controller. The memory controller includes a memory write control unit and a memory read control unit. The memory write control unit generates a write request for any one of the plurality of memories on the basis of a write command from a computer. The memory read control unit generates a read request for any one of the plurality of memories according to priority corresponding to a data processing state of write data related to the write request in the memory write control unit on the basis of a read command from the computer.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: June 8, 2021
    Assignee: SONY CORPORATION
    Inventors: Ken Ishii, Hiroyuki Iwaki, Kenichi Nakanishi, Yasushi Fujinami, Tatsuo Shinbashi
  • Publication number: 20200310681
    Abstract: The order of read access to a memory is appropriately determined. A memory system includes a plurality of memories and a memory controller. The memory controller includes a memory write control unit and a memory read control unit. The memory write control unit generates a write request for any one of the plurality of memories on the basis of a write command from a computer. The memory read control unit generates a read request for any one of the plurality of memories according to priority corresponding to a data processing state of write data related to the write request in the memory write control unit on the basis of a read command from the computer.
    Type: Application
    Filed: April 17, 2017
    Publication date: October 1, 2020
    Inventors: KEN ISHII, HIROYUKI IWAKI, KENICHI NAKANISHI, YASUSHI FUJINAMI, TATSUO SHINBASHI
  • Patent number: 10545804
    Abstract: [Object] To sufficiently reduce frequency of error occurrence in memory cells. [Solution] A reading unit reads read data from a memory cell, the read data including an information bit and reversal information for determining whether or not the information bit has been reversed. In addition, an error detection/correction unit detects the presence or absence of an error in the information bit and corrects the error. A data reversing unit reverses the information bit that has the error corrected and the reversal information. Furthermore, a writing unit writes the reversed information bit and the reversed reversal information in the memory cell.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: January 28, 2020
    Assignee: Sony Corporation
    Inventors: Tatsuo Shinbashi, Keiichi Tsutsui, Hideaki Okubo, Lui Sakai, Kenichi Nakanishi, Yasushi Fujinami
  • Patent number: 10540275
    Abstract: To secure flexibility of the memory extension area which is secured on the memory of the host computer and used by the memory controller. [Solution] A controller memory stores data corresponding to an area allocated to a memory in a memory controller configured to control the memory. An access control unit allocates a partial area of the controller memory to a host memory in a host computer and uses the areas as a memory extension area. The extension area managing unit performs management so that a size of the memory extension area in the host memory is changeable.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: January 21, 2020
    Assignee: Sony Corporation
    Inventors: Hideaki Okubo, Kenichi Nakanishi, Yasushi Fujinami
  • Patent number: 10481971
    Abstract: A data holding characteristic of a memory cell is improved in a memory system in which data is encoded and written to a memory cell. A first candidate parity generation unit generates, as a first candidate parity, a parity for detecting an error in an information section in which a predetermined value is assigned in a predetermined variable area. A second candidate parity generation unit generates, as a second candidate parity, a parity for detecting an error in the information section in which a value different from the predetermined value is assigned in the predetermined variable area. A selection unit selects a parity that satisfies a predetermined condition from among the first and second candidate parities as a selection parity. An output unit outputs a codeword constituted by the information section corresponding to the selection parity and the selection parity.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: November 19, 2019
    Assignee: Sony Corporation
    Inventors: Tatsuo Shinbashi, Kenichi Nakanishi, Yasushi Fujinami, Hiroyuki Iwaki, Ken Ishii, Hideaki Okubo
  • Patent number: 10338984
    Abstract: Detecting a defective cell in a memory in consideration of an error property difference depending on the storage state. A determination unit determines whether there is a possibility of defect for each of unit-of-storages on a memory cell formed with a non-volatile memory. The non-volatile memory undergoes either a reset operation that transitions a state from a low resistive state (LRS) to a high resistive state (HRS) or a set operation that transitions the state from the high resistive state to the low resistive state. The determination unit determines a unit-of-storage in which the number of errors in predetermined one of the reset operation and the set operation has exceeded a predetermined standard, as a unit-of-storage suspected of having a defect.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: July 2, 2019
    Assignee: SONY CORPORATION
    Inventors: Yasushi Fujinami, Kenichi Nakanishi, Tsunenori Shiimoto, Tetsuya Yamamoto, Tatsuo Shinbashi, Hideaki Okubo, Haruhiko Terada, Ken Ishii, Hiroyuki Iwaki, Matatoshi Honjo
  • Patent number: 10310742
    Abstract: The write reliability of a nonvolatile memory is improved by performing accurate verification of write data. In a memory controller of an information processing system, a determination unit determines whether a state of a memory cell after writing data is stable in a nonvolatile memory including the memory cell having an unstable state period after writing data. A verification unit performs verification by comparing read data which is read from the memory cell where the data is written on the basis of a result of the determination, with write data involved in the writing. A write control unit performs writing of the data and rewriting of the write data based on a result of the verification.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: June 4, 2019
    Assignee: Sony Corporation
    Inventor: Yasushi Fujinami
  • Publication number: 20190056884
    Abstract: The write time is to be shortened in a storage device using memories that require different write times from each other, such as nonvolatile memories. In a memory controller including a plurality of write request holding units and a selection unit, the write request holding units holds a write request with respect to each of a plurality of memory modules that require different write times from one another. The selection unit selects one of the plurality of write request holding units in accordance with memory state information indicating whether each of the plurality of memory modules is in a busy state, and causes outputting of the write request.
    Type: Application
    Filed: July 27, 2016
    Publication date: February 21, 2019
    Inventors: KEN ISHII, HIROYUKI IWAKI, KENICHI NAKANISHI, YASUSHI FUJINAMI, TATSUO SHINBASHI
  • Patent number: 10120614
    Abstract: A storage device writes data at a high speed. The storage device is provided with a data area and a control unit. In the data area, a write position is specified by a write address. Also, the control unit writes the data in the write address when instructed to write the data in the write address, and generates an address different from the write address in which the writing is performed as an alternative write address and writes the data in the alternative write address when the writing of the data is unsuccessful.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: November 6, 2018
    Assignee: SONY CORPORATION
    Inventors: Hiroyuki Iwaki, Ken Ishii, Ryoji Ikegaya, Kenichi Nakanishi, Yasushi Fujinami, Naohiro Adachi
  • Publication number: 20180232178
    Abstract: An access speed when a memory controller accesses a memory is improved. Each time any one of two different types of commands is input, a holding unit holds the input command. A priority mode switching unit switches a priority command which should have priority out of the two commands from one of the two commands to the other. A command processing unit preferentially extracts priority commands sequentially from the holding unit, and then sequentially extracts commands which are not the priority commands from the holding unit.
    Type: Application
    Filed: June 15, 2016
    Publication date: August 16, 2018
    Inventors: Hiroyuki Iwaki, Ken Ishii, Yasushi Fujinami, Kennichi Nakanishi, Tatsuo Shinbashi
  • Publication number: 20180143871
    Abstract: A data holding characteristic of a memory cell is improved in a memory system in which data is encoded and written to a memory cell. A first candidate parity generation unit generates, as a first candidate parity, a parity for detecting an error in an information section in which a predetermined value is assigned in a predetermined variable area. A second candidate parity generation unit generates, as a second candidate parity, a parity for detecting an error in the information section in which a value different from the predetermined value is assigned in the predetermined variable area. A selection unit selects a parity that satisfies a predetermined condition from among the first and second candidate parities as a selection parity. An output unit outputs a codeword constituted by the information section corresponding to the selection parity and the selection parity.
    Type: Application
    Filed: April 15, 2016
    Publication date: May 24, 2018
    Inventors: Tatsuo Shinbashi, Kenichi Nakanishi, Yasushi Fujinami, Hiroyuki Iwaki, Ken Ishii, Hideaki Okubo
  • Patent number: 9852812
    Abstract: There is provided a storage apparatus that includes an address obtaining section, and a write processing section. The address obtaining section is configured to obtain a normal write address and an alternative write address before data writing to the normal write address, the normal write address being designated as a destination of the data writing, the alternative write address being used when the data writing is failed. The write processing section is configured to perform the data writing to the normal write address when instructed for the data writing, and perform the data writing to the alternative write address when the data writing to the normal write address is failed.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: December 26, 2017
    Assignee: Sony Corporation
    Inventors: Hiroyuki Iwaki, Ken Ishii, Ryoji Ikegaya, Kenichi Nakanishi, Yasushi Fujinami, Naohiro Adachi
  • Publication number: 20170357572
    Abstract: To secure flexibility of the memory extension area which is secured on the memory of the host computer and used by the memory controller. [Solution] A controller memory stores data corresponding to an area allocated to a memory in a memory controller configured to control the memory. An access control unit allocates a partial area of the controller memory to a host memory in a host computer and uses the areas as a memory extension area. The extension area managing unit performs management so that a size of the memory extension area in the host memory is changeable.
    Type: Application
    Filed: October 8, 2015
    Publication date: December 14, 2017
    Applicant: Sony Corporation
    Inventors: Hideaki Okubo, Kenichi Nakanishi, Yasushi Fujinami