Patents by Inventor Yasushi Kasa
Yasushi Kasa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160259583Abstract: The present invention has an object of providing a storage device capable of making recovery of erased data difficult and erasing the data safely. Provided is a storage device system including a driver controlling an interface between a nonvolatile memory and an external host; and a second controller located between the nonvolatile memory and a first controller, the second controller detecting a logical address of an old data area for a deleted or overwritten file, the second controller detecting a logical address of an old data area for a deleted or overwritten file. The second controller writes invalid data to the logical address of the old data area for the deleted or overwritten file.Type: ApplicationFiled: June 5, 2015Publication date: September 8, 2016Inventors: Yasushi KASA, Moriyoshi NAKASHIMA
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Publication number: 20140281581Abstract: A storage device includes a storage area and connected to a computer for causing a file system to operate. The file system causes a data area for storing contents of a plurality of files and a management area for managing the plurality of files to be secured in the storage area. The storage device includes the storage area; a file system monitor for detecting that the file system has performed an operation of erasing a file; and a controller for, when the file system monitor detects an operation of erasing the file, performing erasure or write to put an area corresponding to the erased file in the storage area into an unrecoverable state.Type: ApplicationFiled: March 17, 2014Publication date: September 18, 2014Applicant: GENUSION, INC.Inventor: Yasushi KASA
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Patent number: 8769377Abstract: Error correcting systems, methods, and devices for non-volatile memory are disclosed. In one embodiment, a non-volatile memory device comprises a data area for storing data, an error correcting code generation section for generating an error correcting code in response to receipt of a code generation command, and an error correcting code area for storing the error correcting code.Type: GrantFiled: May 3, 2013Date of Patent: July 1, 2014Assignee: Spansion LLCInventor: Yasushi Kasa
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Publication number: 20130268823Abstract: Error correcting systems, methods, and devices for non-volatile memory are disclosed. In one embodiment, a non-volatile memory device comprises a data area for storing data, an error correcting code generation section for generating an error correcting code in response to receipt of a code generation command, and an error correcting code area for storing the error correcting code.Type: ApplicationFiled: May 3, 2013Publication date: October 10, 2013Inventor: Yasushi KASA
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Patent number: 8438460Abstract: Error correcting systems, methods, and devices for non-volatile memory are disclosed. In one embodiment, a non-volatile memory device comprises a data area for storing data, an error correcting code generation section for generating an error correcting code in response to receipt of a code generation command, and an error correcting code area for storing the error correcting code.Type: GrantFiled: June 22, 2012Date of Patent: May 7, 2013Assignee: Spansion LLCInventor: Yasushi Kasa
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Publication number: 20120266047Abstract: Error correcting systems, methods, and devices for non-volatile memory are disclosed. In one embodiment, a non-volatile memory device comprises a data area for storing data, an error correcting code generation section for generating an error correcting code in response to receipt of a code generation command, and an error correcting code area for storing the error correcting code.Type: ApplicationFiled: June 22, 2012Publication date: October 18, 2012Inventor: Yasushi KASA
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Patent number: 8225172Abstract: Error correcting systems, methods, and devices for non-volatile memory are disclosed. In one embodiment, a non-volatile memory device comprises a data area for storing data, an error correcting code generation section for generating an error correcting code in response to receipt of a code generation command, and an error correcting code area for storing the error correcting code. The non-volatile memory device further comprises a detector circuit for detecting the generating of the error correcting code, and a read section for correcting the data stored in the data area based on the error correcting code upon the detecting of the generation of the error correcting code by the detector circuit, where the code generation command is forwarded by a memory controller when the data are is filled with the data beyond a threshold level.Type: GrantFiled: June 16, 2008Date of Patent: July 17, 2012Assignee: Spansion LLCInventor: Yasushi Kasa
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Patent number: 7679150Abstract: A semiconductor device is provided which includes a pair of metal interconnections (B, C) provided above a semiconductor substrate (10), a program layer (20) provided over the pair of metal interconnections (B, C) and in which an opening (21) may be selectively formed in the program layer (20) on the basis of programming information, and a read circuit (40) reading the programming information by determining whether such an opening (21) is formed in the program layer (20) by utilizing an electrostatic capacitance between the pair of metal interconnections (B, C). The program layer (20) may be made of a material having a dielectric constant higher than that of air or the program layer (20) may be made of a conductor or a material having a dielectric constant lower than that of air.Type: GrantFiled: April 27, 2006Date of Patent: March 16, 2010Assignee: Spansion LLCInventor: Yasushi Kasa
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Publication number: 20090158123Abstract: Error correcting systems, methods, and devices for non-volatile memory are disclosed. In one embodiment, a non-volatile memory device comprises a data area for storing data, an error correcting code generation section for generating an error correcting code in response to receipt of a code generation command, and an error correcting code area for storing the error correcting code.Type: ApplicationFiled: June 16, 2008Publication date: June 18, 2009Inventor: Yasushi KASA
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Patent number: 7206241Abstract: The semiconductor device of the present invention includes at least one dummy cell of a programmed state proximately located to an edge of a reference cell array. Thus, the leak current does not flow when a data of the cell on the edge of the reference cell array is read out. The memory cell located around the center of the reference cell array has neighboring cells of the programmed state, and the leak current can be prevented when the data is read out from all the reference cells. Thus, the reference current can be supplied stably.Type: GrantFiled: May 11, 2005Date of Patent: April 17, 2007Assignee: Spansion LLCInventors: Kazunari Kido, Yasushi Kasa, Minoru Yamashita, Kazuhiro Kurihara, Hiroaki Wada
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Publication number: 20070052064Abstract: A semiconductor device is provided which includes a pair of metal interconnections (B, C) provided above a semiconductor substrate (10), a program layer (20) provided over the pair of metal interconnections (B, C) and in which an opening (21) may be selectively formed in the program layer (20) on the basis of programming information, and a read circuit (40) reading the programming information by determining whether such an opening (21) is formed in the program layer (20) by utilizing an electrostatic capacitance between the pair of metal interconnections (B, C). The program layer (20) may be made of a material having a dielectric constant higher than that of air or the program layer (20) may be made of a conductor or a material having a dielectric constant lower than that of air.Type: ApplicationFiled: April 27, 2006Publication date: March 8, 2007Inventor: Yasushi Kasa
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Patent number: 7012838Abstract: A nonvolatile semiconductor memory device includes a plurality of blocks each having a nonvolatile memory cell array, and a program potential generating circuit which supplies a program potential to the nonvolatile memory cell array, wherein the program potential generating circuit adjusts the program potential according to a first address signal selecting one of the blocks and a second address signal indicating a position of a write-accessed memory cell in the noted one of the blocks.Type: GrantFiled: August 1, 2003Date of Patent: March 14, 2006Assignee: Fujitsu LimitedInventors: Yasushi Kasa, Jyoji Kato
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Publication number: 20050276112Abstract: The semiconductor device of the present invention includes at least one dummy cell of a programmed state proximately located to an edge of a reference cell array. Thus, the leak current does not flow when a data of the cell on the edge of the reference cell array is read out. The memory cell located around the center of the reference cell array has neighboring cells of the programmed state, and the leak current can be prevented when the data is read out from all the reference cells. Thus, the reference current can be supplied stably.Type: ApplicationFiled: May 11, 2005Publication date: December 15, 2005Inventors: Kazunari Kido, Yasushi Kasa, Minoru Yamashita, Kazuhiro Kurihara, Hiroaki Wada
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Patent number: 6865133Abstract: A memory circuit has a plurality of blocks which further comprises a plurality of regular sectors and a spare sector, wherein each sector further comprises a plurality of memory cells, and when a regular sector in a first block is defective, this defective regular sector is replaced with a spare sector in a second block. And responding to an address to be supplied, the regular sector corresponding to the supplied address in the first block and the spare selector in the second block are selected simultaneously during a first period, and after the first period, selection of one of the regular sector and the spare sector is maintained according to the result of redundancy judgment on whether the supply address matches with the redundant address.Type: GrantFiled: September 2, 2003Date of Patent: March 8, 2005Assignee: Fujitsu LimitedInventors: Yoshihiro Tsukidate, Kazuhiro Kurihara, Yasushi Kasa, Tsutomu Nakai, Andy Cheung
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Publication number: 20040109371Abstract: A memory circuit has a plurality of blocks which further comprises a plurality of regular sectors and a spare sector, wherein each sector further comprises a plurality of memory cells, and when a regular sector in a first block is defective, this defective regular sector is replaced with a spare sector in a second block. And responding to an address to be supplied, the regular sector corresponding to the supplied address in the first block and the spare selector in the second block are selected simultaneously during a first period, and after the first period, selection of one of the regular sector and the spare sector is maintained according to the result of redundancy judgment on whether the supply address matches with the redundant address.Type: ApplicationFiled: September 2, 2003Publication date: June 10, 2004Inventors: Yoshihiro Tsukidate, Kazuhiro Kurihara, Yasushi Kasa, Tsutomu Nakai, Andy Cheung
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Publication number: 20040062078Abstract: A nonvolatile semiconductor memory device includes a plurality of blocks each having a nonvolatile memory cell array, and a program potential generating circuit which supplies a program potential to the nonvolatile memory cell array, wherein the program potential generating circuit adjusts the program potential according to a first address signal selecting one of the blocks and a second address signal indicating a position of a write-accessed memory cell in the noted one of the blocks.Type: ApplicationFiled: August 1, 2003Publication date: April 1, 2004Applicant: FUJITSU LIMITEDInventors: Yasushi Kasa, Jyoji Kato
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Patent number: 6662262Abstract: A simultaneous operation flash memory capable of providing double protection to An OTP sector. The preferred simultaneous operation flash memory comprises an OTP write-protect CAM, which is in a programmed state if the OTP sector is write-protected. In addition, the preferred simultaneous flash memory further includes an OTP sector lock CAM that is electrically connected with the OTP write-protect CAM. The OTP sector lock CAM is used to lock the OTP write-protect CAM in the programmed state, which, in turn, will designate the OTP sector as read only.Type: GrantFiled: October 19, 1999Date of Patent: December 9, 2003Assignees: Advanced Micro Devices, Inc., Fujitsu LimitedInventors: Yasushi Kasa, Johnny Chung-Lee Chen, Guowei Wang, Tiao-Hua Kuo
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Patent number: 6646920Abstract: A semiconductor memory device includes a plurality of word lines and a plurality of bit lines. A plurality of memory cells, each formed of a MIS transistor, are disposed at intersections of the word lines and the bit lines. The threshold voltages of the MIS transistors being externally electrically controllable according to charges to be injected to floating gates thereof. The floating gates of the MIS transistors being simultaneously discharged to collectively erase the memory cells. A first row decoder applies a normal voltage to a selected word line to select memory cells connected to the selected word line, when reading data. A second row decoder applies a predetermined source voltage to sources of memory cells connected to the selected word line, and applies an unselected state establishing voltage to the sources of memory cells, including those overerased by the collective erasing, connected to unselected word lines, when reading data.Type: GrantFiled: October 7, 2002Date of Patent: November 11, 2003Assignee: Fujitsu LimitedInventors: Nobuaki Takashina, Yasushi Kasa, Kiyoshi Itano
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Publication number: 20030198083Abstract: A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.Type: ApplicationFiled: November 26, 2002Publication date: October 23, 2003Applicant: Fujitsu LimitedInventors: Takao Akaogi, Nobuaki Takashina, Yasushi Kasa, Kiyoshi Itano, Hiromi Kawashima, Minoru Yamashita, Shouichi Kawamura
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Patent number: 6633949Abstract: A bank selector encoder comprises a partition indicator circuit having a plurality of partition boundary indicator terminals, a plurality of inverters arranged in a plurality of columns, with each column of the inverters coupled to a respective one of a plurality of columns of ROM cells in a ROM array and a plurality of bank selector code outputs coupled to respective columns of the inverters. The partition boundary indicator terminals are capable of designating a memory partition boundary to identify an upper memory bank and a lower memory bank. The bank selector encoder is capable of generating an identifying bank selector code for each of a plurality of the predetermined memory partition boundaries. The bank selector encoder outputs code bits of a bank selector code based upon the partition boundary indicator terminals.Type: GrantFiled: June 26, 2001Date of Patent: October 14, 2003Assignees: Advanced Micro Devices, Inc., Fujitsu LimitedInventors: Tiao-Hua Kuo, Yasushi Kasa, Nancy Leong, Johnny Chen, Michael Van Buskirk