Patents by Inventor Yasushi Kasatani
Yasushi Kasatani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6861370Abstract: A bump formation method and a bump formation apparatus can be gained wherein the reliability of a semiconductor device is enhanced by removing satellites that may be generated by a solder jet-type nozzle. This bump formation method is a method forming a bump on an electrode pad (2) provided on a work piece (1) by using a nozzle (21) of a solder jet system that discharges a molten solder drop (8) and is provided with the coating layer formation step of forming a coating layer (3, 5, 6, 7) having a portion that temporarily protects the work piece (1), the solder drop discharging step of discharging a molten solder drop (8) from the nozzle (21) toward the electrode pad (2) after the coating layer formation step and the coating layer removal step of removing the coating layer (3, 5, 6, 7) in the region other than the region beneath the solder drop formed in the solder drop discharging step.Type: GrantFiled: October 23, 2000Date of Patent: March 1, 2005Assignee: Renesas Technology Corp.Inventor: Yasushi Kasatani
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Patent number: 6798056Abstract: A semiconductor module includes a substrate having a pad electrode on a surface, a lower layer semiconductor package mounted on the substrate, and an upper layer semiconductor package mounted on the substrate while arranged in a position substantially overlying the former. The pad electrodes connected to the leads of these semiconductor packages are arranged alternately. The lead has a dambar residual portion. An inner surface of a lead downward portion of the upper layer semiconductor package is positioned outside an outer surface of a lead downward portion of the lower layer semiconductor package.Type: GrantFiled: August 30, 2002Date of Patent: September 28, 2004Assignee: Renesas Technology Corp.Inventors: Tetsuya Matsuura, Yasushi Kasatani, Kazunari Michii
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Patent number: 6717275Abstract: A plurality of substrates are stacked on top of each other. A flexible cable serially connects the substrates. Semiconductor packages are mounted on the surfaces of the substrates. An adhesive material bonds adjoining semiconductor packages and holds the semiconductor packages in place with respect to each other. The bottommost substrate is provided with external leads by which the semiconductor module is mounted on the motherboard.Type: GrantFiled: April 30, 2002Date of Patent: April 6, 2004Assignee: Renesas Technology Corp.Inventors: Tetsuya Matsuura, Yasushi Kasatani, Tadashi Ichimasa
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Patent number: 6670701Abstract: A semiconductor module achieving higher density of the semiconductor module itself as well as of being disposed in an area-efficient manner relative to another electronic component, such as a mother board and the like. The semiconductor module includes a mounting substrate having, on an underside, a solder ball for connecting to an interconnection of a mother board and semiconductor packages mounted in multiple layers on the top side of the mounting substrate and connected to electrodes on the mounting substrate.Type: GrantFiled: December 4, 2001Date of Patent: December 30, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuya Matsuura, Yasushi Kasatani, Kazunari Michii, Hajime Maeda
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Publication number: 20030174481Abstract: A semiconductor module includes a substrate having a pad electrode on a surface, a lower layer semiconductor package mounted on the substrate, and an upper layer semiconductor package mounted on the substrate while arranged in a position substantially overlying the former. The pad electrodes connected to the leads of these semiconductor packages are arranged alternately. The lead has a dambar residual portion. An inner surface of a lead downward portion of the upper layer semiconductor package is positioned outside an outer surface of a lead downward portion of the lower layer semiconductor package.Type: ApplicationFiled: August 30, 2002Publication date: September 18, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuya Matsuura, Yasushi Kasatani, Kazunari Michii
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Patent number: 6617695Abstract: Lands for mounting are located on the upper and lower surfaces of a substrate. External electrodes are exposed at a rear surface of a package body. An IC package is mounted by bonding the lands for mounting to the external electrodes. Lands for external connection are connected to the lands for mounting. The lands for external connection are located outside of the IC package. Solder bumps are connected to one side of the lands for external mounting. Thus, a semiconductor device for a semiconductor module is provided.Type: GrantFiled: November 3, 2000Date of Patent: September 9, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Yasushi Kasatani
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Patent number: 6590286Abstract: A land grid array semiconductor device provides greater positioning accuracy for an external electrode with respect to a mounting substrate. External electrodes are arranged on one surface of a substrate in area array. The external electrode includes an external electrode pad and an external electrode interconnection. Each external electrode pad includes a first pad layer having a cylindrical shape and a second pad layer covering the surface of the first pad layer and having a conical shape.Type: GrantFiled: October 23, 2001Date of Patent: July 8, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Makio Okada, Yasushi Kasatani, Tomoaki Hashimoto
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Publication number: 20030080438Abstract: A plurality of substrates are stacked on top of each other. A flexible cable serially connects the substrates. Semiconductor packages are mounted on the surfaces of the substrates. An adhesive material bonds adjoining semiconductor packages and holds the semiconductor packages in place with respect to each other. The bottommost substrate is provided with external leads by which the semiconductor module is mounted on the motherboard.Type: ApplicationFiled: April 30, 2002Publication date: May 1, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuya Matsuura, Yasushi Kasatani, Tadashi Ichimasa
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Publication number: 20030051893Abstract: The present invention has a purpose to provide a surface-mounting connector for electrically connecting with the terminals of the semiconductor module board by pinching thereof, without soldering. The surface-mounting connector includes a supporting member made of insulating material having a first and second surfaces, and a top-surface connecting lead pin and a bottom-surface connecting lead pin. The lead pins are disposed in parallel with a predetermined gap and supported by the supporting member. The top-surface connecting lead pin and the bottom-surface connecting lead pin have one end portions bent in a predetermined direction at different positions away from the first surface of the supporting member.Type: ApplicationFiled: August 19, 2002Publication date: March 20, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Tadashi Ichimasa, Tetsuya Matsuura, Yasushi Kasatani
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Publication number: 20030052393Abstract: A semiconductor device comprises a package; one or a plurality of chips sealed in the package; and leads having inner parts electrically connected to the chip or the chips in the package, and outer parts extending outside the package. The package has an upper elevated part having a top surface, and terraced surfaces formed at a level below a level of the top surface. The leads are provided with joining parts to which leads included in another semiconductor device to be put on top of the package are to be bonded, respectively, on the terraced surface. The joining parts of the leads have a width greater than a width of other parts of the leads.Type: ApplicationFiled: March 27, 2002Publication date: March 20, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Kazunari Michii, Yasushi Kasatani
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Patent number: 6492714Abstract: A pair of IC packages are placed in an opening of a substrate, and have straight leads laterally extending. IC package mounting lands correspondingly connected to the straight leads are arranged on upper and lower faces of a substrate. External connection lands serving as external connection terminals are disposed on extended lines along which the straight leads are drawn out, and correspondingly connected to the straight leads. The external connection lands are configured by: first-group external connection lands arranged along the side of integrated circuit packages; and second-group external connection lands arranged outside the first-group external connection lands. The first-group external connection lands and the second-group external connection lands are arranged in a staggered pattern.Type: GrantFiled: June 27, 2000Date of Patent: December 10, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Yasushi Kasatani
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Publication number: 20020153608Abstract: A main object of the present invention is to provide a land grid array type semiconductor device which has been improved to provide greater positioning accuracy for an external electrode with respect to a mounting substrate. An external electrode is arranged in one surface of a substrate in area array. The external electrode includes an external electrode pad and an external electrode interconnection. The external electrode pad includes a first pad layer formed in a cylinder shape and a second pad layer formed to cover the surface of the first pad layer in a cone shape.Type: ApplicationFiled: October 23, 2001Publication date: October 24, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Makio Okada, Yasushi Kasatani, Tomoaki Hashimoto
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Publication number: 20020100965Abstract: A semiconductor module can be produced that is capable of achieving higher density of the semiconductor module itself as well as of being disposed in an area-efficient manner to another electronic component such as a mother substrate and the like. The semiconductor module includes a mounting substrate having on the underside a solder ball for connecting to the interconnection of a mother substrate and a plurality of semiconductor packages mounted in multiple layers on the surface side of the mounting substrate and connected to electrodes provided on the mounting substrate.Type: ApplicationFiled: December 4, 2001Publication date: August 1, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuya Matsuura, Yasushi Kasatani, Kazunari Michii, Hajime Maeda
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Patent number: 5363274Abstract: A memory card having no ordinary type circuit board and a reduced thickness. Insulating layers are disposed on reverse surfaces of a pair of metallic panels, and circuit patterns are formed on the insulating layers. A plurality of electronic parts are mounted on the metallic panels by, for example, being soldered to the circuit patterns. The pair of metallic panels on which the electronic parts are mounted are fitted and bonded to openings formed in a frame of the card so that the electronic parts are accommodated inside the frame facing each other.Type: GrantFiled: February 19, 1992Date of Patent: November 8, 1994Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Makoto Omori, Jun Ohbuchi, Hajime Maeda, Yasushi Kasatani
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Patent number: 5306541Abstract: A printed circuit board has a staggered array of mounting pads on a surface thereof for supporting a terminal board. A solder material is provided on the staggered array and then a terminal board having a corresponding array of pads is placed on the printed circuit board. The solder material is heated and then cooled, whereby the terminal board is fixed to the printed circuit board without causing an electric short between pads.Type: GrantFiled: January 15, 1993Date of Patent: April 26, 1994Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Yasushi Kasatani
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Patent number: 5024605Abstract: A connecting electrode includes an electrode substrate, a contact having a buttonhook-shaped section provided on the electrode substrate, a convex surface of the contact projecting from the electrode substrate for deformation by a battery and a projection from the substrate beside the convex surface for controlling the amount of deformation of the contact by a battery.Type: GrantFiled: July 13, 1990Date of Patent: June 18, 1991Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yasushi Kasatani, Toru Tachikawa
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Patent number: 4868714Abstract: An IC card having a package in which a semiconductor device is accommodated, a plurality of electrode terminals disposed on a surface of the package near the front end thereof in the direction in which the IC card is inserted into a connector in an external device, a shutter supported on the surface of a front portion of the package for exposing and covering the electrode terminals, the shutter having a width smaller than that of the package as measured in the direction perpendicular to the direction of insertion into the connector, a pair of guide projections formed on the shutter at both-sides thereof to extend into the package, the guide projections functioning to open the shutter by abutting against a pair of shutter receiving pins disposed in the insertion hole of the connector when the package is inserted into the connector, and a pair of guide grooves adapted to guide the guide projections, the guide grooves being formed in both sides of the front portion of the surface of the package to be within theType: GrantFiled: March 30, 1988Date of Patent: September 19, 1989Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshinobu Banjo, Yasuhiro Murasawa, Shigeo Onoda, Yasushi Kasatani
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Patent number: 4864116Abstract: A mechanism for connecting an IC card and an external device to each other, having: a plurality of electrode terminals formed on a package of the IC card incorporating a semiconductor device and used to connect the semiconductor device to the external device; at least one engagement recess and/or engagement projection formed on the package of the IC card; and a connector provided in the external device. This connector is provided with an insertion hole, a plurality of electrode-contacting pieces disposed in the insertion hole and capable of contacting the plurality of electrode terminals of the IC card when the IC card is inserted into the connector, and at least one engagement projection and/or engagement recess formed inside the insertion hole and capable of engaging the engagement recess and/or engagement projection formed on the package to enable a particular type of the IC card to be inserted into the connector.Type: GrantFiled: March 10, 1988Date of Patent: September 5, 1989Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshinobu Banjo, Tetsuya Ueda, Shigeo Onoda, Yasushi Kasatani
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Patent number: 4838804Abstract: A connection mechanism for connecting an IC card and an external device to each other, having: a plurality of electrode terminals formed on the IC card package in which a semiconductor device is incorporated, the electrode terminals being adapted to connect the semiconductor device to the external device; a pair of engagement recesses formed on the package of the IC card; and a connector provided in the external device, the connector having a card receiving portion into which the IC card is inserted, a plurality of electrode-contacting pieces disposed inside the card receiving portion and capable of contacting the plurality of electrode terminals of the IC card when the IC card is inserted into the card receiving portion to a predetermined position, and a pair of retaining members disposed on the card receiving portion and capable of advancing toward or retreating from the engagement recesses of the IC card and resiliently engaging the engagement recesses so as to retain the IC card at the predetermined positType: GrantFiled: March 25, 1988Date of Patent: June 13, 1989Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshinobu Banjo, Tetsuya Ueda, Shigeo Onoda, Yasushi Kasatani