Abstract: Provided are a multilayer structure in which crystal defects due to stress concentration in a semiconductor layer caused by an insulator film are prevented and a semiconductor device using the multilayer structure, the multilayer structure and the semiconductor device that are particularly useful for power devices. A multilayer structure in which an insulator film is arranged on a part of a semiconductor film, wherein the semiconductor film has a corundum structure and contains a crystalline oxide semiconductor containing one or two or more metals selected from groups 9 and 13 of the periodic table, and wherein the insulator film has a taper angle of 20° or less.

Abstract: An epitaxial wafer production method, including forming a gettering epitaxial film containing silicon and carbon on a silicon substrate under reduced pressure using a reduced pressure CVD apparatus, and forming a silicon epitaxial film on the gettering epitaxial film. This provides a low-cost, low-contamination carbon-containing epitaxial wafer, and a method for producing such an epitaxial wafer.

Abstract: To suppress an unnatural movement of a moving object at a connection point when a plurality of pieces of video data are connected to each other. A frame acquisition unit 22 acquires pieces of frame data captured at the same time, from the pieces of video data input from cameras C1 and C2. A prohibited-region setting unit 24 sets a prohibited region that is not set as a calculation target when a seam is calculated, based on a position of an object detected in an overlap region between adjacent pieces of frame data and a movement direction of the object. A seam calculation unit 25 calculates a seam between pieces of frame data adjacent to each other, without setting a pixel included in the prohibited region as the calculation target of seam calculation. A connection-frame output unit 26 connects pieces of frame data in accordance with the seam and outputs connection frame data 15.

Abstract: Objects are tracked in real time in a composed video acquired by joining a plurality of videos. A grouping candidate determining unit extracts objects present within an overlapping area, in which pieces of frame data are overlapped, among objects that have been detected and tracked in each of a plurality of pieces of frame data that were captured at the same time as candidate objects. A grouping unit arranges a plurality of candidate objects of which a degree of overlapping is equal to or larger than a predetermined threshold as a group, and an integration unit assigns integration object IDs to groups and objects that have not been grouped.

Abstract: Self-test circuits of memory devices disclosed herein may include circuitry that adjusts the correspondence between logical and physical addresses to match pre-repair mapping of memory locations. That is, if a memory device has been repaired by remapping logical addresses to new physical addresses, the circuitry of the test circuit restores the pre-repair mapping of the memory device in some examples. In some examples, an unused global column redundancy data path may be repurposed to provide repair information to the self-test circuit to implement the pre-repair mapping.

Abstract: An apparatus includes a memory chip including a plurality of fuse units, and a controller chip. Each fuse unit includes a fuse array having a plurality of fuse cells, a first register, and a second register. The controller is configured to set the fuse address in the second register included in selected one or more of the plurality of fuse units, set the match signal in the first register included in the selected one or more of the plurality of fuse units, and send a blow signal to the memory chip. Each of the selected one or more of the plurality of fuse units is configured to blow one of the plurality of fuse cells selected by the fuse address stored in the second register responsive to the blow signal.

Abstract: A cell capture apparatus comprises a centrifugal container that can be mounted in a centrifuge, and that has a space in which a test liquid containing target cells is held, and an inner surface that defines the space; and a cell adhesion layer that is disposed on the inner surface and adsorbs the target cells in the test liquid.

Abstract: To more reliably control synchronous between pieces of video/audio data from a plurality of imaging system devices. A synchronous control unit 15 that synchronizes a plurality of pieces of video/audio data transmitted individually from a plurality of imaging system devices 2 includes a frame acquisition unit 151 configured to acquire a plurality of pieces of frame data from the pieces of video/audio data and assign a frame timestamp based on an acquisition time to each of the plurality of pieces of frame data, for each of the pieces of the video/audio data, and a frame shaping unit 152 configured to assign a new frame timestamp to the plurality of pieces of frame data based on a value of the frame timestamp so that start times of the plurality of pieces of frame data that are close in time among the plurality of pieces of video/audio data are equal to each other, and time intervals between the plurality of pieces of frame data are equal to each other.

Abstract: A synchronous shift of video/audio data between a plurality of display system devices is suppressed. A synchronous control device includes a coded-data adjustment unit 312 or a video and audio data adjustment unit 314 configured to perform frame adjustment based on a predetermined frame adjustment instruction by inserting predetermined frame data into a plurality of pieces of frame data in a chronological order or deleting a piece of frame data from the plurality of pieces of frame data, a video and audio data output unit 315 configured to sequentially output each piece of frame data subjected to the frame adjustment, and a video and audio data output time-point adjustment unit 316 configured to compare a reference time point for outputting each piece of the frame data with an output time point at which each piece of the frame data is output.

Abstract: A memory cell comprises first, second, third, and fourth transistors individually comprising a transistor gate. First and second ferroelectric capacitors individually have one capacitor electrode elevationally between the transistor gates of the first, second, third, and fourth transistors. Other memory cells are disclosed, as are arrays of memory cells.

Abstract: Methods, systems, and devices for sequential voltage control for a memory device are described. A memory device may have various voltage sources that support different voltage levels used in various operations of the memory device. Voltage sources of a memory device may be disabled under some circumstances, such as when the memory device is idled, or operated in a low-power or powered-down mode, among other circumstances. In accordance with examples as disclosed herein, voltage sources of a memory device or memory die may be sequentially enabled or sequentially disabled. For example, voltage sources may be enabled in an order from voltage sources having relatively higher nominal voltages to voltage sources having relatively lower voltages, or disabled in an order from voltage sources having relatively lower nominal voltages to voltage sources having relatively higher voltages.

Abstract: Disclosed herein is an apparatus that includes a fuse array circuit including a plurality of fuse sets each assigned to a corresponding one of a plurality of fuse addresses and configured to operatively store a fuse data, and a first circuit configured to generate and sequentially update a fuse address to sequentially read the fuse data from the plurality of fuse sets. The first circuit is configured to change a frequency of updating the fuse address based on a first signal.

Abstract: Methods and apparatuses for erasing data on a plurality of ferroelectric memory cells in a memory cell array in a memory apparatus are disclosed. An example apparatus includes: a memory cell array including a first plurality of word lines; a digit line; and a plurality of ferroelectric memory cells; a control circuit that provides a section select signal and a word line select signal to select a second plurality of word lines among the first plurality of word lines responsive to an address; and an address decoder that activates the second plurality of word lines. Each ferroelectric memory cell includes: a ferroelectric capacitor having a first terminal coupled to a cell plate node and a second terminal coupled to a selection circuit that couples the digit line to the second terminal responsive to a signal on a corresponding word line of the second plurality of word lines.

Abstract: Methods, systems, and devices for system and method for reading and writing memory management data through a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.

Abstract: Disclosed herein is an apparatus that includes a fuse array circuit including a plurality of fuse sets each assigned to a corresponding one of a plurality of fuse addresses and configured to operatively store a fuse data, and a first circuit configured to generate and sequentially update a fuse address to sequentially read the fuse data from the plurality of fuse sets. The first circuit is configured to change a frequency of updating the fuse address based on a first signal.

Abstract: Methods, systems, and devices for grouping power supplies for a power saving mode are described to configure a memory device with groups of internal power supplies whose voltage levels may be successively modified according to a group order signaled by an on-die timer. For example, when the memory device enters a deep sleep mode, respective voltage levels of a first group of internal power supplies may be modified to respective external power supply voltage levels at a first time, respective voltage levels of a second group of internal power supplies may be modified to respective external power supply voltage levels at a second time, and so on. When the memory device exits the deep sleep mode, the groups of internal voltage supplies may be modified from the respective external power supply voltage levels to respective operational voltage levels in a group order that is opposite to the entry group order.

Abstract: Apparatuses and methods related to power domain boundary protection in memory. A number of embodiments can include using a voltage detector to monitor a floating power supply voltage used to power a number of logic components while a memory device operates in a reduced power mode, and responsive to the voltage detector detecting that the floating power supply voltage reaches a threshold value while the memory device is in the reduced power mode, providing a control signal to protection logic to prevent a floating output signal driven from one or more of the logic components from being provided across a power domain boundary to one or more of a different number of logic components.

Abstract: Methods, systems, and devices for system and method for reading and writing memory management data through a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.

Abstract: Methods, systems, and devices related to access schemes for access line faults in a memory device are described. In one example, a method may include isolating a first word line of a section of a memory device from a voltage source (e.g., a deselection voltage source) during a first portion of a period when the first word line is deselected, and coupling the first word line with the voltage source during a second portion of the period when the first word line is deselected based on determining that an access operation is performed during the second portion of the period when the word line is deselected. In some examples, the method may include identifying that the first word line is associated with a fault, such as a short circuit fault with a digit line of the memory device.

Abstract: Methods, systems, and devices for grouping power supplies for a power saving mode are described to configure a memory device with groups of internal power supplies whose voltage levels may be successively modified according to a group order signaled by an on-die timer. For example, when the memory device enters a deep sleep mode, respective voltage levels of a first group of internal power supplies may be modified to respective external power supply voltage levels at a first time, respective voltage levels of a second group of internal power supplies may be modified to respective external power supply voltage levels at a second time, and so on. When the memory device exits the deep sleep mode, the groups of internal voltage supplies may be modified from the respective external power supply voltage levels to respective operational voltage levels in a group order that is opposite to the entry group order.