Patents by Inventor Yasushi Okuda

Yasushi Okuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190233987
    Abstract: A water injection apparatus for a water jet loom, includes a weft insertion nozzle for weft insertion of a weft yarn by injection water, a weft insertion pump pumping water into the weft insertion nozzle, a water storage tank storing water introduced into the weft insertion pump, and a suction pipe passing water from the water storage tank into the weft insertion pump. The water injection apparatus includes an auxiliary water supply unit that is provided separately from the weft insertion pump and can supply water to the suction pipe. At least when the weft insertion pump sucks water, the auxiliary water supply unit supplies water to the suction pipe.
    Type: Application
    Filed: January 3, 2019
    Publication date: August 1, 2019
    Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
    Inventors: Yasushi YAMAUCHI, Koichi TSUJIMOTO, Kouichi HATTORI, Kenji SUMIYA, Taijirou OKUDA
  • Publication number: 20190078779
    Abstract: In a soot blower, a heat transfer tube of a heat exchanger is arranged inside a pressure vessel, and gas for cleaning is injected toward the heat transfer tube from an injection pipe movable into and out of the pressure vessel. The soot blower includes a cylindrical casing provided to surround an insertion hole on the pressure vessel side into which the injection pipe is inserted, to extend outside the pressure vessel, the injection pipe being inserted into an inside of the casing; a support part provided inside the casing to guide movement of the injection pipe and to ensure airtightness between the casing and the injection pipe; and a gas supplying device provided immediately close to the support part to generate a jet stream of gas in a portion of the injection pipe that projects to the pressure vessel side.
    Type: Application
    Filed: March 28, 2017
    Publication date: March 14, 2019
    Applicants: MITSUBISHI HITACHI POWER SYSTEMS, LTD., MHI PLANT CORPORATION
    Inventors: Gen Sakashita, Yoshinori Koyama, Takashi Yamamoto, Kenta Haari, Yasunari Shibata, Masashi Kitada, Yasushi Okuda, Masami Tsuda, Satoru Murai
  • Patent number: 6753222
    Abstract: A method for forming a semiconductor device is provided that allows a desirable semiconductor device to be obtained by preventing a gate electrode of a non-volatile semiconductor memory from having an abnormal shape and the surfaces of high concentration source and drain regions of the non-volatile semiconductor memory from being worn away. The method includes a first step of forming a non-volatile semiconductor memory in a first region of a substrate of the semiconductor device and a second step of forming a semiconductor device in a second region on the substrate. The non-volatile semiconductor memory includes a first gate including a tunnel insulating film, a floating gate electrode, a capacitor insulating film, and a control gate electrode, and the semiconductor device includes a second gate including a gate insulating film and a gate electrode.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: June 22, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Ken Mimuro, Hiroyuki Doi, Yasushi Okuda
  • Patent number: 6657893
    Abstract: A memory transistor and a select transistor are disposed side by side on a semiconductor substrate between source/drain diffusion layers thereof, with an intermediate diffusion layer interposed therebetween. The memory transistor includes: a gate insulating film having such a thickness as to allow tunneling current to pass therethrough; a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The select transistor includes a gate insulating film and a select gate electrode. Tunneling current, allowing electrons to pass through the gate insulating film under the floating gate electrode, is utilized during the removal and injection of electrons from/into the floating gate electrode. As a result, higher reliability can be attained and rewriting can be performed at a lower voltage. Also, since the select transistor is provided, reading can also be performed at a lower voltage.
    Type: Grant
    Filed: January 22, 2002
    Date of Patent: December 2, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Keita Takahashi, Masafumi Doi, Hiroyuki Doi, Nobuyuki Tamura, Yasushi Okuda
  • Publication number: 20030082878
    Abstract: A method for forming a semiconductor device is provided that allows a desirable semiconductor device to be obtained by preventing a gate electrode of a non-volatile semiconductor memory from having an abnormal shape and the surfaces of high concentration source and drain regions of the non-volatile semiconductor memory from being worn away. The method includes a first step of forming a non-volatile semiconductor memory in a first region of a substrate of the semiconductor device and a second step of forming a semiconductor device in a second region on the substrate. The non-volatile semiconductor memory includes a first gate including a tunnel insulating film, a floating gate electrode, a capacitor insulating film, and a control gate electrode, and the semiconductor device includes a second gate including a gate insulating film and a gate electrode.
    Type: Application
    Filed: October 15, 2002
    Publication date: May 1, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Ken Mimuro, Hiroyuki Doi, Yasushi Okuda
  • Patent number: 6472281
    Abstract: A gate insulator film and a gate electrode are formed on an Si substrate, and a CVD insulator film is deposited thereon to cover the gate electrode. Then, arsenic ions are implanted into the Si substrate from above the CVD insulator film to form LDD layers. After sidewall spacers have been formed over the side faces of the gate electrode with the CVD insulator film interposed therebetween, source/drain layers are formed. Since the LDD layers are formed by implanting dopant ions through the CVD insulator film, the passage of arsenic ions through the ends of the gate electrode can be suppressed. As a result, a semiconductor device suitable for miniaturization can be formed, while suppressing deterioration in insulating properties of the gate oxide film due to the passage of dopant ions through the ends of the gate electrode.
    Type: Grant
    Filed: January 28, 1999
    Date of Patent: October 29, 2002
    Assignee: Matsushita Electronics Corporation
    Inventors: Hiroyuki Doi, Yasushi Okuda, Keita Takahashi, Nobuyuki Tamura
  • Publication number: 20020064071
    Abstract: A memory transistor and a select transistor are disposed side by side on a semiconductor substrate between source/drain diffusion layers thereof, with an intermediate diffusion layer interposed therebetween. The memory transistor includes: a gate insulating film having such a thickness as to allow tunneling current to pass therethrough; a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The select transistor includes a gate insulating film and a select gate electrode. Tunneling current, allowing electrons to pass through the gate insulating film under the floating gate electrode, is utilized during the removal and injection of electrons from/into the floating gate electrode. As a result, higher reliability can be attained and rewriting can be performed at a lower voltage. Also, since the select transistor is provided, reading can also be performed at a lower voltage.
    Type: Application
    Filed: January 22, 2002
    Publication date: May 30, 2002
    Applicant: Matsushita Electronics Corporation
    Inventors: Keita Takahashi, Masafumi Doi, Hiroyuki Doi, Nobuyuki Tamura, Yasushi Okuda
  • Patent number: 6377490
    Abstract: A memory transistor and a select transistor are disposed side by side on a semiconductor substrate between source/drain diffusion layers thereof, with an intermediate diffusion layer interposed therebetween. The memory transistor includes: a gate insulating film having such a thickness as to allow tunneling current to pass therethrough; a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The select transistor includes a gate insulating film and a select gate electrode. Tunneling current, allowing electrons to pass through the gate insulating film under the floating gate electrode, is utilized during the removal and injection of electrons from/into the floating gate electrode. As a result, higher reliability can be attained and rewriting can be performed at a lower volt age. Also, since the select transistor is provided, reading c an also be performed at a lower voltage.
    Type: Grant
    Filed: October 3, 2000
    Date of Patent: April 23, 2002
    Assignee: Matsushita Electronics Corporation
    Inventors: Keita Takahashi, Masafumi Doi, Hiroyuki Doi, Nobuyuki Tamura, Yasushi Okuda
  • Patent number: 6323663
    Abstract: A retainer board, holding a semiconductor wafer having a plurality of integrated circuit terminals for testing a semiconductor chip, is provided in confronting relation to a probe sheet having a plurality of probe terminals electrically connected to their corresponding integrated circuit terminals. An insulating substrate, having wiring electrically connected to the plural probe terminals, is provided on the probe sheet in opposed relation to the retainer board. An elastic member is interposed between the probe sheet and the insulating substrate. The retainer board and the probe sheet are brought into so closer relationship that each integrated circuit terminal of the semiconductor wafer held by the retainer board is electrically connected to its corresponding probe terminal of the probe sheet.
    Type: Grant
    Filed: September 16, 1999
    Date of Patent: November 27, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshirou Nakata, Toshio Yamada, Atsushi Fujiwara, Isao Miyanaga, Shin Hashimoto, Yukiharu Uraoka, Yasushi Okuda, Kenzou Hatada
  • Publication number: 20010026982
    Abstract: A gate insulator film and a gate electrode are formed on an Si substrate, and a CVD insulator film is deposited thereon to cover the gate electrode. Then, arsenic ions are implanted into the Si substrate from above the CVD insulator film to form LDD layers. After sidewall spacers have been formed over the side faces of the gate electrode with the CVD insulator film interposed therebetween, source/drain layers are formed. Since the LDD layers are formed by implanting dopant ions through the CVD insulator film, the passage of arsenic ions through the ends of the gate electrode can be suppressed. As a result, a semiconductor device suitable for miniaturization can be formed, while suppressing deterioration in insulating properties of the gate oxide film due to the passage of dopant ions through the ends of the gate electrode.
    Type: Application
    Filed: January 28, 1999
    Publication date: October 4, 2001
    Inventors: HIROYUKI DOI, YASUSHI OKUDA, KEITA TAKAHASHI, NOBUYUKI TAMURA
  • Patent number: 6169307
    Abstract: A memory transistor and a select transistor are disposed side by side on a semiconductor substrate between source/drain diffusion layers thereof, with an intermediate diffusion layer interposed therebetween. The memory transistor includes: a gate insulating film having such a thickness as to allow tunneling current to pass therethrough; a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The select transistor includes a gate insulating film and a select gate electrode. Tunneling current, allowing electrons to pass through the gate insulating film under the floating gate electrode, is utilized during the removal and injection of electrons from/into the floating gate electrode. As a result, higher reliability can be attained and rewriting can be performed at a lower voltage. Also, since the select transistor is provided, reading can also be performed at a lower voltage.
    Type: Grant
    Filed: December 8, 1998
    Date of Patent: January 2, 2001
    Assignee: Matsushita Electronics Corporation
    Inventors: Keita Takahashi, Masafumi Doi, Hiroyuki Doi, Nobuyuki Tamura, Yasushi Okuda
  • Patent number: 6005401
    Abstract: A retainer board, holding a semiconductor wafer having a plurality of integrated circuit terminals for testing a semiconductor chip, is provided in confronting relation to a probe sheet having a plurality of probe terminals electrically connected to their corresponding integrated circuit terminals. An insulating substrate, having wiring electrically connected to the plural probe terminals, is provided on the probe sheet in opposed relation to the retainer board. An elastic member is interposed between the probe sheet and the insulating substrate. The retainer board and the probe sheet are brought into so closer relationship that each integrated circuit terminal of the semiconductor wafer held by the retainer board is electrically connected to its corresponding probe terminal of the probe sheet.
    Type: Grant
    Filed: April 14, 1997
    Date of Patent: December 21, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshirou Nakata, Toshio Yamada, Atsushi Fujiwara, Isao Miyanaga, Shin Hashimoto, Yukiharu Uraoka, Yasushi Okuda, Kenzou Hatada
  • Patent number: 5945834
    Abstract: A retainer board, holding a semiconductor wafer having a plurality of integrated circuit terminals for testing a semiconductor chip, is provided in confronting relation to a probe sheet having a plurality of probe terminals electrically connected to their corresponding integrated circuit terminals. An insulating substrate, having wiring electrically connected to the plural probe terminals, is provided on the probe sheet in opposed relation to the retainer board. An elastic member is interposed between the probe sheet and the insulating substrate. The retainer board and the probe sheet are brought into so closer relationship that each integrated circuit terminal of the semiconductor wafer held by the retainer board is electrically connected to its corresponding probe terminal of the probe sheet.
    Type: Grant
    Filed: February 29, 1996
    Date of Patent: August 31, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshirou Nakata, Toshio Yamada, Atsushi Fujiwara, Isao Miyanaga, Shin Hashimoto, Yukiharu Uraoka, Yasushi Okuda, Kenzou Hatada
  • Patent number: 5715196
    Abstract: An array of non-volatile memory cells arranged in rows and columns is provided. Each memory cell is composed of a transistor made up of a gate, a source, and drain and a capacitance section. Each memory cell is connected to a row decoder through a wordline, to a column decoder through a bitline, and to a source decoder through a sourceline. Arranged in a path extending from a bitline to a sourceline through a transistor is an anisotropic resistance section, e.g., a diode, exhibiting different voltage-current characteristics for different levels of voltages applied thereacross. Because of such arrangement, leakage current occurring to a deselected memory cell in a reading operation can be reduced or can be eliminated. Read errors due to leakage current can be avoided and the power consumption can be reduced.
    Type: Grant
    Filed: July 19, 1996
    Date of Patent: February 3, 1998
    Assignee: Matsushita Electric Industrial, Co., Ltd.
    Inventors: Yoshinori Odake, Akira Asai, Yasushi Okuda, Toshiki Mori, Ichirou Nakao
  • Patent number: 5698614
    Abstract: A fluorescent ink composition which comprises:(a) an organic solvent which comprises propylene glycol monomethyl ether as a solvent:(b) a solution type fluorescent pigment dissolved in the organic solvent; and(c) a ketone resin.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: December 16, 1997
    Assignee: Sakura Color Products Corporation
    Inventors: Hiroaki Ueda, Masakazu Yokoi, Yasushi Okuda
  • Patent number: 5640345
    Abstract: Provided between a control gate electrode and a channel region of the EEPROM memory cell is a capacitor. Formed on the channel region are a first gate dielectric layer of silicon oxide, a first carrier capture layer of silicon nitride, a carrier migration layer of n.sup.31 polysilicon, a second carrier capture layer of silicon nitride, and a second gate dielectric layer of silicon oxide. The carrier capture state of the carrier capture layer is changed to generate a polarization state in the capacitor, and the generated polarization state is held as data. The gate dielectric layer is not destroyed since the movement of carriers is limited to within the capacitor, and by adjusting the carrier bound energy, low-voltage drive can be accomplished.
    Type: Grant
    Filed: July 12, 1996
    Date of Patent: June 17, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasushi Okuda, Takashi Hori, Ichiro Nakao
  • Patent number: 5627779
    Abstract: An array of non-volatile memory cells arranged in rows and columns is provided. Each memory cell is composed of a transistor made up of a gate, a source, and drain and a capacitance section. Each memory cell is connected to a row decoder through a wordline, to a column decoder through a bitline, and to a source decoder through a sourceline. Arranged in a path extending from a bitline to a sourceline through a transistor is an anisotropic resistance section, e.g., a diode, exhibiting different voltage-current characteristics for different levels of voltages applied thereacross. Because of such arrangement, leakage current occurring to a deselected memory cell in a reading operation can be reduced or can be eliminated. Read errors due to leakage current can be avoided and the power consumption can be reduced.
    Type: Grant
    Filed: July 21, 1995
    Date of Patent: May 6, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshinori Odake, Akira Asai, Yasushi Okuda, Toshiki Mori, Ichirou Nakao
  • Patent number: 5510639
    Abstract: A non-volatile semiconductor memory cell having a novel structure is provided. The memory cell has a ring-shaped channel region formed on a semiconductor substrate, a drain region formed in a zone surrounded by the channel region, and a source region formed outside the channel region. The cell further includes a first gate insulation layer formed on the substrate in such a manner as to cover the boundary between the channel region and the drain region, a ring-shaped floating gate electrode formed on the first gate insulation layer, a second gate insulation layer formed on the floating gate electrode; and a control gate electrode which is capacitive-coupled with the floating gate via the second gate insulation layer.
    Type: Grant
    Filed: February 9, 1995
    Date of Patent: April 23, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasushi Okuda, Yoshinori Odake, Ichiro Nakao, Youhei Ichikawa
  • Patent number: 5418187
    Abstract: A method of manufacturing semiconductor devices, which realizes miniaturization, a higher aspect ratio of a via hole, a higher yield and reliability, and a high degree of controllability, by completely filling the via hole by performing heat treatment on an electrically conductive thin film in a vacuum atmosphere. The method involves extending an electrically conductive layer into an electrically insulating layer arranged on the electrically conductive layer including the steps of forming an electrically conductive film on a side wall of a via hole extending in the electrically insulating layer from the electrically conductive layer toward the outside of the electrically insulating layer, and heating the electrically conductive film and the electrically conductive layer so that the electrically conductive film flows into the via hole and the electrically conductive layer projects into the via hole.
    Type: Grant
    Filed: February 28, 1994
    Date of Patent: May 23, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Isao Miyanaga, Yasushi Okuda
  • Patent number: 5359554
    Abstract: A semiconductor device is provided comprising a nonvolatile memory cell through which an LSI and a higher operating speed are achieved. A drain region, an insulating layer partly overlaying the drain region, and a gate electrode formed on the insulating layer are formed on a semiconductor substrate thereby making up a memory cell without a source region. An energy gap between the conduction and valence bands of a semiconductor section including the drain region and the semiconductor substrate is preset to a value corresponding to a first set voltage difference between the drain and the gate. The energy gap between the valence bands (or the conduction bands) of the insulating layer and the semiconductor section at the interface between the semiconductor section and the insulating layer is preset to a value corresponding to a second set voltage difference between the drain and the substrate.
    Type: Grant
    Filed: June 30, 1992
    Date of Patent: October 25, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshinori Odake, Yasushi Okuda