Patents by Inventor Yasutaka Nakashiba

Yasutaka Nakashiba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200168545
    Abstract: A first semiconductor chip and a second semiconductor chip are stacked such that a first inductor and a second inductor face each other. An insulating sheet is disposed between the first semiconductor chip and the second semiconductor chip. The sealing member seals the first semiconductor chip, the second semiconductor chip, and the insulating sheet. The sealing member is disposed both between the insulating sheet and the first semiconductor chip and between the insulating sheet and the second semiconductor chip.
    Type: Application
    Filed: October 15, 2019
    Publication date: May 28, 2020
    Inventors: Shinichi UCHIDA, Akio ONO, Shinichi KUWABARA, Yasutaka NAKASHIBA
  • Publication number: 20200161278
    Abstract: The control system according to embodiments includes a switching element, a control unit controlling the conductive state of the switching element, and a first capacitor storing charge supplied to the control unit. The first capacitor and the control unit are connected with each other via the switching element.
    Type: Application
    Filed: October 10, 2019
    Publication date: May 21, 2020
    Inventors: Shinichi KUWABARA, Yasutaka NAKASHIBA, Tetsuya IIDA
  • Publication number: 20200161284
    Abstract: The semiconductor module includes a semiconductor chip and a semiconductor chip. The semiconductor chip includes an optical device such as an optical waveguide, an optical receiver, and a grating coupler, and a wiring formed over the optical device. The semiconductor chip includes a semiconductor element such as a MISFET formed in the semiconductor substrate, and a wiring formed over the semiconductor element. a top surface of the semiconductor chip is laminated to a top surface of the semiconductor chip such that the wirings are in direct contact with each other. In the semiconductor substrate, a through hole having a circular shape in plan view is formed, in the through hole, an insulating film is formed as a cladding layer, and the semiconductor substrate surrounded by the through hole constitutes an optical waveguide.
    Type: Application
    Filed: October 10, 2019
    Publication date: May 21, 2020
    Inventors: Tetsuya IIDA, Yasutaka NAKASHIBA
  • Patent number: 10656442
    Abstract: In an optical waveguide supplied with electricity by using a heater, miniaturization of the device is achieved by enhancing heat dissipation efficiency and heat resistance. In a modulator including an optical waveguide formed on an insulating film, a first interlayer insulating film that covers the optical waveguide, a heater formed on the first interlayer insulating film, and a second interlayer insulating film that covers the heater, a heat conducting portion adjacent to the optical waveguide and the heater and penetrating the first and second interlayer insulating films is formed.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: May 19, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Tetsuya Iida, Yasutaka Nakashiba, Shinichi Kuwabara
  • Patent number: 10578805
    Abstract: An optical waveguide formed at the same layer as that of a microscopic optical device and a spot size converter largely different in size are integrally formed. A semiconductor device has an optical waveguide part functioning as a spot size converter. The optical waveguide part includes a plurality of optical waveguide bodies penetrating through an interlayer insulation layer in the thickness direction.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: March 3, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasutaka Nakashiba, Shinichi Watanuki
  • Publication number: 20200043847
    Abstract: A semiconductor device includes a first semiconductor chip on which a first circuit is formed and a second semiconductor chip on which two circuits are formed. In the first semiconductor chip, a first inductor on the transmitting side electrically connected with the first circuit and a second inductor on the receiving side electrically connected with the second circuit via the bonding wire are formed. In plan view, the first inductor and the second inductor are disposed so as not to overlap each other, and are arranged along each other.
    Type: Application
    Filed: July 8, 2019
    Publication date: February 6, 2020
    Inventors: Shinichi KUWABARA, Yasutaka NAKASHIBA, Teruhiro KUWAJIMA
  • Patent number: 10527872
    Abstract: A low reflectance film with a second reflectance (50% or lower) lower than a first reflectance is formed between an optical directional coupler and a first-layer wiring with the first reflectance. Thus, even when the first-layer wiring is formed above the optical directional coupler, the influence of the light reflected by the first-layer wiring on the optical signal propagating through the first optical waveguide and the second optical waveguide of the optical directional coupler can be reduced. Accordingly, the first-layer wiring can be arranged above the optical directional coupler, and the restriction on the layout of the first-layer wiring is relaxed.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: January 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroyuki Kunishima, Yasutaka Nakashiba, Masaru Wakabayashi, Shinichi Watanuki
  • Publication number: 20190391327
    Abstract: The semiconductor device has an optical waveguide formed on a substrate, a first conductor film formed in the same layer as the optical waveguide, an insulating film formed on the first conductor film, a second conductor film formed on the insulating film, and a first interlayer insulating film formed on the substrate so as to cover the optical waveguide and the second conductor film. The semiconductor device includes a first contact hole reaching the first conductor film, a second contact hole reaching the second conductor film, a first contact plug formed in the first contact hole, and a second contact plug formed in the second contact hole. The first conductor film is disposed between the first contact plugs and the board, but the second conductor film is not disposed between the first contact plugs and the board.
    Type: Application
    Filed: May 14, 2019
    Publication date: December 26, 2019
    Inventors: Shinichi WATANUKI, Yasutaka NAKASHIBA
  • Publication number: 20190393148
    Abstract: In a semiconductor device, a semiconductor substrate includes a bulk layer, a buried oxide layer provided in at least a partial region on the bulk layer, and a surface single crystal layer on the buried oxide layer. An inductor is provided above a main surface side of the semiconductor substrate on which the surface single crystal layer is disposed. To increase a Q value of the inductor, a ground shield is an impurity region formed in the bulk layer below the inductor and below the buried oxide layer.
    Type: Application
    Filed: June 11, 2019
    Publication date: December 26, 2019
    Inventors: Shinichi UCHIDA, Yasutaka NAKASHIBA
  • Publication number: 20190391325
    Abstract: The semiconductor device includes an optical waveguide WG1 formed in a planar manner, and a three-dimensional optical waveguide WG2 optically connected with the optical waveguide WG1 and including a curved shape.
    Type: Application
    Filed: June 11, 2019
    Publication date: December 26, 2019
    Inventors: Tetsuya IIDA, Yasutaka NAKASHIBA
  • Publication number: 20190372676
    Abstract: The semiconductor module includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes an optical device such as an optical waveguide and wiring formed over the optical device. The second semiconductor chip include semiconductor elements such as MISFET, and wiring formed over the semiconductor elements.
    Type: Application
    Filed: May 9, 2019
    Publication date: December 5, 2019
    Inventors: Tetsuya IIDA, Yasutaka NAKASHIBA
  • Publication number: 20190371727
    Abstract: The semiconductor device includes a first semiconductor substrate, a first wiring layer, a second wiring layer, a second semiconductor substrate, a first conductive portion, and a second conductive portion. The first wiring layer includes a first electrode pad and a first inductor electrically connected with each other. The second wiring layer includes a second inductor and a second electrode pad electrically connected with each other. The first conductive portion is formed in the second semiconductor substrate, the second wiring layer, and the first wiring layer so as to reach the first electrode pad from the back surface of the second semiconductor substrate. The second conductive portion is formed in the second semiconductor substrate and the second wiring layer so as to reach the second electrode pad from the back surface of the second semiconductor substrate. The first inductor and the second inductor are disposed so as to face each other.
    Type: Application
    Filed: May 9, 2019
    Publication date: December 5, 2019
    Inventors: Shinichi Kuwabara, Yasutaka Nakashiba
  • Patent number: 10497654
    Abstract: A semiconductor device includes an annular seal ring formed in a seal ring region surrounding a circuit forming region. The seal ring includes a BOX layer, an n-type semiconductor layer, and an annular electrode portion comprised of multiple layers of wirings. The electrode portion is electrically connected with the n-type semiconductor layer through a plug electrode.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: December 3, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Shinichi Uchida, Yasutaka Nakashiba
  • Patent number: 10475918
    Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: November 12, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Tohru Kawai, Yasutaka Nakashiba, Yutaka Akiyama
  • Patent number: 10466415
    Abstract: A semiconductor device including an optical waveguide and a p-type semiconductor portion is configured as follows. The optical waveguide includes: a first semiconductor layer formed on an insulating layer; an insulating layer formed on the first semiconductor layer; and a second semiconductor layer formed on the insulating layer. The p-type semiconductor portion includes the first semiconductor layer. The film thickness of the p-type semiconductor portion is smaller than that of the optical waveguide. By forming the insulating layer between the first semiconductor layer and the second semiconductor layer, control of the film thicknesses of the optical waveguide and the p-type semiconductor portion is facilitated. Specifically, when the unnecessary second semiconductor layer is removed by etching in a step of forming the p-type semiconductor portion, the insulating layer which is the lower layer functions as an etching stopper, and the film thickness of the p-type semiconductor portion can be easily adjusted.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: November 5, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Yasutaka Nakashiba, Shinichi Watanuki
  • Patent number: 10459162
    Abstract: To provide a semiconductor device including a low-loss optical waveguide. The optical waveguide included in the semiconductor device has a core layer covered with first and second clad layers having respectively different refractive indices. A portion of the core layer is covered at a first ratio, that is, a ratio of the first clad layer to the second clad layer and at the same time, a second ratio, that is, a ratio of the second clad layer to the first clad layer. At this time, the first ratio and the second ratio are each a finite value more than 0.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: October 29, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuya Iida, Yasutaka Nakashiba
  • Publication number: 20190317276
    Abstract: According to the present invention, a first semiconductor chip includes a semiconductor substrate, an optical waveguide formed on an upper surface of the semiconductor substrate, and a concave portion formed in the semiconductor substrate in a region that differs from a region in which the optical waveguide is formed. A second semiconductor chip includes a compound semiconductor substrate, and a light emitting unit formed on an upper surface of the compound semiconductor substrate and emitting a laser beam. The second semiconductor chip is mounted in the concave portion of the first semiconductor chip, and a pedestal which is an insulating film is formed between a bottom surface of the concave portion and a back surface of the compound semiconductor substrate.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 17, 2019
    Inventors: Tetsuya IIDA, Yasutaka NAKASHIBA
  • Patent number: 10446543
    Abstract: A semiconductor device of the present invention includes, in a region 1C, a top electrode made by a semiconductor layer of an SOI substrate, a capacitive insulating film made by an insulating layer, a bottom electrode made by a supporting board, and a lead part (a high-concentration impurity region of an n type) of the bottom electrode coupled to the supporting board. An SOI transistor in a region 1B is formed over a main surface of the semiconductor layer over the insulating layer as a thin film, and threshold voltage can be adjusted by applying a voltage to a well arranged on the rear face side of the insulating layer.
    Type: Grant
    Filed: October 29, 2017
    Date of Patent: October 15, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Shinichi Uchida, Takafumi Kuramoto, Yasutaka Nakashiba
  • Patent number: 10418321
    Abstract: A compact semiconductor device with an isolator. The semiconductor device includes two chips, namely a first semiconductor chip and a second semiconductor chip which are stacked with the main surfaces of the semiconductor chips partially facing each other. A first coil and a second coil which are formed in the first semiconductor chip and the second semiconductor chip respectively are arranged to face each other so as to be magnetically coupled during operation of the semiconductor device. The pair of first and second coils make up an isolator. The first coil is arranged in a manner to overlap part of the circuit region of the first semiconductor chip in plan view and the second coil is arranged in a manner to overlap part of the circuit region of the second semiconductor chip in plan view.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: September 17, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Kuwabara, Tetsuya Iida, Yasutaka Nakashiba
  • Patent number: 10416382
    Abstract: In an optical waveguide section of an SIS type having a configuration of stacking a second semiconductor layer over a first semiconductor layer with a dielectric layer interposed, the first semiconductor layer is electrically coupled to a first electrode at a first lead-out section where the second semiconductor layer is not stacked. Further, the second semiconductor layer is electrically coupled to a second electrode at a second lead-out section not overlapping with the first semiconductor layer. As a result, when a contact hole for forming the second electrode is formed by dry etching, the dielectric layer between the first semiconductor layer and the second semiconductor layer is not damaged or broken and hence short-circuit failure between the first semiconductor layer and the second semiconductor layer can be prevented. The reliability of the optical waveguide section therefore can be improved.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: September 17, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasutaka Nakashiba, Shinichi Watanuki