Abstract: A memory controller includes: a memory access control circuit which receives a write command and write data from a processor and controls a writing operation to a memory; and a number-of-writing-operations control circuit which performs control to execute the writing operation to the memory multiple times, based on the write command and the write data.

Abstract: An information processing device includes: a processor that executes processing of data; and a memory module that includes a first memory in which a plurality of memory chips each storing the data are mounted in layers, and a memory controller that controls the first memory, wherein the memory controller: inspects the data; executes correction processing of the data when a single bit error is detected; determines, when a single bit error is detected in a memory chip corresponding to a first layer, a first inspection area in a memory chip corresponding to another layer, based on a first location at which the single bit error occurs; and executes first inspection of data in the first inspection area.

Abstract: A module includes a substrate, a first wiring, a second wiring, and an interlayer connection section. The substrate includes a first surface facing a first direction, a second surface facing a second direction opposite to the first direction, and an inner surface of a hole extending between the first surface and the second surface. The first wiring is provided on the first surface. The second wiring is provided on the second surface. The interlayer connection section includes a first conductor provided on the inner edge, connected to the first wiring and the second wiring, thinner than the first wiring, and thinner than the second wiring, and a second conductor disposed in the hole and electrically connected to the first conductor.

Abstract: A memory controller includes: a memory access control circuit which receives a write command and write data from a processor and controls a writing operation to a memory; and a number-of-writing-operations control circuit which performs control to execute the writing operation to the memory multiple times, based on the write command and the write data.

Abstract: An information processing device includes: a processor that executes processing of data; and a memory module that includes a first memory in which a plurality of memory chips each storing the data are mounted in layers, and a memory controller that controls the first memory, wherein the memory controller: inspects the data; executes correction processing of the data when a single bit error is detected; determines, when a single bit error is detected in a memory chip corresponding to a first layer, a first inspection area in a memory chip corresponding to another layer, based on a first location at which the single bit error occurs; and executes first inspection of data in the first inspection area.

Abstract: A battery-shaped wireless device includes a housing having an exterior shape of a standardized battery, a wireless module disposed in the housing and configured to generate a wireless signal, and a control circuit configured to cause the wireless module to generate the wireless signal. The battery-shaped wireless device can fit in a space designed for a standardized battery.

Abstract: A monitoring processor controls a plurality of electronic devices that each include a cooling fan that cools inside of a casing and a fan controller that controls the cooling fan. The monitoring processor includes a fan speed controller that performs control on the fan controllers of the respective electronic devices to change rotation speed of at least any cooling fan based on pieces of sound pressure information of sounds emitted by the respective electronic devices measured by a sound pressure measuring device.

Abstract: A disclosed information processing system includes a plurality of information processing devices cooled by cooling water; a plurality of chillers each configured to circulate the cooling water to and from the plurality of the information processing devices; a flow monitor unit configured to monitor a total flow volume, where the total flow volume being a sum of a flow volume of each cooling water of the plurality of the chillers; and adjustment units each provided to each of the chiller, where the adjustment unit being configured to adjust an individual flow volume of the cooling water in the corresponding chiller, such that the total flow volume monitored by the flow monitor unit becomes equal to a set value suitable for cooling the plurality of the information processing devices.

Abstract: A cable connection method for an electronic device (such as a blade server), which includes: placing a jig in an arrangement location (such as a rack) in which the electronic device is to be arranged, and holding by a holder at least one of a cable and a connector member connected with the cable, the holder provided in a location in the jig corresponding to a connector attachment member in the electronic device; arranging the electronic device in the arrangement location; and connecting the connector member with the connector attachment member.

Abstract: A monitoring processor controls a plurality of electronic devices that each include a cooling fan that cools inside of a casing and a fan controller that controls the cooling fan. The monitoring processor includes a fan speed controller that performs control on the fan controllers of the respective electronic devices to change rotation speed of at least any cooling fan based on pieces of sound pressure information of sounds emitted by the respective electronic devices measured by a sound pressure measuring device.

Abstract: To improve the processing efficiency and throughput by performing only a recovery process in read-accessing to a memory even when an address parity error has occurred in write-accessing to the memory, a selector is provided to select one of write data and a parity-bitted address for writing to the memory. If an address parity error has detected, the selector selects the parity-bitted address, in which the address parity error has occurred, instead of write data to be written to the memory during the write-accessing thereto. This address parity error processing method is particularly useful when applied to an information processor, such as a computer system, including a storage (memory).

Abstract: To improve the processing efficiency and throughput by performing only a recovery process in read-accessing to a memory even when an address parity error has occurred in write-accessing to the memory, a selector is provided to select one of write data and a parity-bitted address for writing to the memory. If an address parity error has detected, the selector selects the parity-bitted address, in which the address parity error has occurred, instead of write data to be written to the memory during the write-accessing thereto.

Abstract: A TMR unit connects a plurality of processors by a bus and simultaneously executes the same processing operation. Among the plurality of processors, one of them is a master and the remaining processors are slaves. Information formed by only the master processor is outputted to the bus. Each processor has a multiplex control circuit. The multiplex control circuit compares output information formed by itself with bus information outputted to the bus, thereby detecting a failure and allowing an internal circuit to execute necessary processes.

Abstract: A round robin arbitration circuit arbitrating N requests has a register storing one of N values, a priority encoder selecting one of N priority patterns according to the value in the register and assigning priorities to the requests based on the selected priority pattern, thereby conducting arbitration between the requests, a circuit updating the value in the register among the N values in a predetermined order synchronously with the arbitration, and a circuit updating the value in the register among the N values in the predetermined order at regular intervals that are asynchronous with the arbitration. At the regular intervals that are asynchronous with the arbitration, a jump is made in the predetermined updating order of the values to be set in the register. Accordingly, even if live-lock occurs, it will be solved when such a jump is made to make the number of priority patterns disagree with the number of requests issued in a loop.

Abstract: A TMR unit connects a plurality of processors by a bus and simultaneously executes the same processing operation. Among the plurality of processors, one of them is a master and the remaining processors are slaves. Information formed by only the master processor is outputted to the bus. Each processor has a multiplex control circuit. The multiplex control circuit compares output information formed by itself with bus information outputted to the bus, thereby detecting a failure and allowing an internal circuit to execute necessary processes.

Abstract: In an access processing system in an information processor, the information processor includes: an access device (10, 11) for generating an access request signal; an accessed device (13) provided with a memory means (30) that is accessed by the access device (10, 11); and an address bus (14) that has the access device and accessed device connected with the information processor at least by the address bus (14).The access processing system is processed such that, if an access request is produced, when the access request signal does not require all bits in the address bus (14), an unused bit in the address bus (14) is loaded with write data to deliver it to the accessed device (13).

Abstract: In a clock control circuit for suppressing a clock pulse in a plurality of devices which operate in synchronization with each other, the clock control circuit detects first and second clock suppress conditions, generates a first clock suppress signal in all the devices based on the detection of the first clock suppress condition, generates a second clock suppress signal in a particular device based on the detection of the first or second clock suppress conditions, transmits the clock suppress signals to all the devices, and suppresses the clock pulse in all the devices based on the first and second clock suppress signals. The second clock suppress signal suppresses the clock pulse after it is suppressed by the first clock suppress signal, and continues to suppress the clock pulse until a suppression release signal is received.