Patents by Inventor Yasutoshi Yamada
Yasutoshi Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11094367Abstract: Provided are a sub-amplifier, a switching device and a semiconductor device capable of simultaneously reading or writing many data items, while suppressing an increase in chip surface area, by using a single end signal line. A sub-amplifier SAP comprises: a first pre-charge circuit 110 that releases pre-charges of a pair of local wires LIOT/LIOB; a local inversion drive circuit 120 that, on the basis of a write signal WT, inverts and transfers write data to a sense amplifier SA from a main wire MIOB via one of the local wires LIOT/LIOB; a local non-inversion drive circuit 130 that, on the basis of the write signal WT, transfers the write data to the sense amplifier SA from the main wire MIOB via the other one of the local wires LIOT/LIOB; and a main inversion drive circuit 140 that, on the basis of a read signal RT, inverts and transfers read data to the main wire MIOB from one of the local wires LIOT/LIOB.Type: GrantFiled: September 11, 2017Date of Patent: August 17, 2021Assignee: ULTRAMEMORY INC.Inventor: Yasutoshi Yamada
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Patent number: 10861530Abstract: The purpose of the present invention is to achieve a system for solving a row hammer issue without significantly increasing a DRAM chip area. A semiconductor storage device comprises: a memory unit including a plurality of memory cells; an address latch unit that receives an active command and an address therefor, and latches and holds the address every time the active command is received; a refresh control unit that, when receiving a refresh command, instructs a memory access control unit to carry out a regular refresh operation while instructing the memory access control unit to carry out an interrupt refresh operation for an address near the address latched by the address latch unit; and the memory access control unit that carries out the regular refresh operation and the interrupt refresh operation for the memory unit on the basis of the instruction from the refresh control unit.Type: GrantFiled: April 8, 2016Date of Patent: December 8, 2020Assignee: Ultramemory Inc.Inventors: Yasutoshi Yamada, Ryuji Takishita
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Publication number: 20200286546Abstract: Provided are a sub-amplifier, a switching device and a semiconductor device capable of simultaneously reading or writing many data items, while suppressing an increase in chip surface area, by using a single end signal line. A sub-amplifier SAP comprises: a first pre-charge circuit 110 that releases pre-charges of a pair of local wires LIOT/LIOB; a local inversion drive circuit 120 that, on the basis of a write signal WT, inverts and transfers write data to a sense amplifier SA from a main wire MIOB via one of the local wires LIOT/LIOB; a local non-inversion drive circuit 130 that, on the basis of the write signal WT, transfers the write data to the sense amplifier SA from the main wire MIOB via the other one of the local wires LIOT/LIOB; and a main inversion drive circuit 140 that, on the basis of a read signal RT, inverts and transfers read data to the main wire MIOB from one of the local wires LIOT/LIOB.Type: ApplicationFiled: September 11, 2017Publication date: September 10, 2020Inventor: Yasutoshi YAMADA
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Patent number: 10714151Abstract: The purposes of the present invention are: to provide a layered semiconductor device capable of improving production yield; and to provide a method for producing said layered semiconductor device. This layered semiconductor device has, layered therein, a plurality of semiconductor chips, a reserve semiconductor chip which is used as a reserve for the semiconductor chips, and a control chip for controlling the operating states of the plurality of semiconductor chips and the operating state of the reserve semiconductor chip. In such a configuration, the semiconductor chips and the reserve semiconductor chip include contactless communication units and operating switches. The semiconductor chips and the reserve semiconductor chip are capable of contactlessly communicating with another of the semiconductor chips via the contactless communication units.Type: GrantFiled: November 25, 2019Date of Patent: July 14, 2020Assignee: ULTRAMEMORY INC.Inventors: Yasutoshi Yamada, Kouji Uemura, Takao Adachi
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Publication number: 20200090708Abstract: The purposes of the present invention are: to provide a layered semiconductor device capable of improving production yield; and to provide a method for producing said layered semiconductor device. This layered semiconductor device has, layered therein, a plurality of semiconductor chips, a reserve semiconductor chip which is used as a reserve for the semiconductor chips, and a control chip for controlling the operating states of the plurality of semiconductor chips and the operating state of the reserve semiconductor chip. In such a configuration, the semiconductor chips and the reserve semiconductor chip include contactless communication units and operating switches. The semiconductor chips and the reserve semiconductor chip are capable of contactlessly communicating with another of the semiconductor chips via the contactless communication units.Type: ApplicationFiled: November 25, 2019Publication date: March 19, 2020Inventors: Yasutoshi YAMADA, Kouji UEMURA, Takao ADACHI
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Patent number: 10529385Abstract: A layered semiconductor device capable of improving production yield and a method for producing the layered semiconductor device. The layered semiconductor device has, layered therein, a plurality of semiconductor chips, a reserve semiconductor chip which is used as a reserve for the semiconductor chips, and a control chip for controlling the operating states of the plurality of semiconductor chips and the operating state of the reserve semiconductor chip. The semiconductor chips and the reserve semiconductor chip include contactless communication units and operating switches, and are capable of contactlessly communicating with another of the semiconductor chips via the contactless communication units. The control chip controls the operating states of the semiconductor chips by switching the operating switches of the semiconductor chips, and controls the operating state of the reserve semiconductor chip by switching the operating switch of the reserve semiconductor chip.Type: GrantFiled: December 22, 2016Date of Patent: January 7, 2020Assignee: ULTRAMEMORY INC.Inventors: Yasutoshi Yamada, Kouji Uemura, Takao Adachi
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Publication number: 20190122722Abstract: The purpose of the present invention is to achieve a system for solving a row hammer issue without significantly increasing a DRAM chip area. A semiconductor storage device comprises: a memory unit including a plurality of memory cells; an address latch unit that receives an active command and an address therefor, and latches and holds the address every time the active command is received; a refresh control unit that, when receiving a refresh command, instructs a memory access control unit to carry out a regular refresh operation while instructing the memory access control unit to carry out an interrupt refresh operation for an address near the address latched by the address latch unit; and the memory access control unit that carries out the regular refresh operation and the interrupt refresh operation for the memory unit on the basis of the instruction from the refresh control unit.Type: ApplicationFiled: April 8, 2016Publication date: April 25, 2019Inventors: Yasutoshi YAMADA, Ryuji TAKISHITA
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Publication number: 20190043537Abstract: A layered semiconductor device capable of improving production yield and a method for producing the layered semiconductor device. The layered semiconductor device has, layered therein, a plurality of semiconductor chips, a reserve semiconductor chip which is used as a reserve for the semiconductor chips, and a control chip for controlling the operating states of the plurality of semiconductor chips and the operating state of the reserve semiconductor chip. The semiconductor chips and the reserve semiconductor chip include contactless communication units and operating switches, and are capable of contactlessly communicating with another of the semiconductor chips via the contactless communication units. The control chip controls the operating states of the semiconductor chips by switching the operating switches of the semiconductor chips, and controls the operating state of the reserve semiconductor chip by switching the operating switch of the reserve semiconductor chip.Type: ApplicationFiled: December 22, 2016Publication date: February 7, 2019Applicant: ULTRAMEMORY INC.Inventors: Yasutoshi YAMADA, Kouji UEMURA, Takao ADACHI
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Patent number: 8988958Abstract: A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes.Type: GrantFiled: June 17, 2014Date of Patent: March 24, 2015Assignee: PS4 Luxco S.a.r.l.Inventors: Kazuhiko Kajigaya, Soichiro Yoshida, Yasutoshi Yamada
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Patent number: 8982652Abstract: A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes.Type: GrantFiled: November 13, 2012Date of Patent: March 17, 2015Assignee: PS4 Luxco S.a.r.l.Inventors: Kazuhiko Kajigaya, Soichiro Yoshida, Yasutoshi Yamada
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Patent number: 8976612Abstract: A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes.Type: GrantFiled: November 1, 2012Date of Patent: March 10, 2015Assignee: PS4 Luxco S.a.r.l.Inventors: Kazuhiko Kajigaya, Soichiro Yoshida, Yasutoshi Yamada
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Patent number: 8971140Abstract: A semiconductor device comprises a sense amplifier circuit amplifying a signal transmitted through the bit line, first/second data lines transmitting the signal amplified by the sense amplifier circuit, a read amplifier circuit driven by a first voltage and amplifying the signal; first/second switch circuits controlling connection between the above components, first/second voltage setting circuits setting the second/third data lines to a second voltage lower than the first voltage. A predetermined voltage obtained by adding the second voltage to a threshold voltage of a transistor in the second/third switch circuit is applied to the gate terminal thereof, and ends of the data lines are connected to the source and drain terminals thereof.Type: GrantFiled: July 6, 2012Date of Patent: March 3, 2015Assignee: PS4 Luxco S.a.r.l.Inventors: Soichiro Yoshida, Kazuhiko Kajigaya, Yasutoshi Yamada
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Patent number: 8944735Abstract: The invention provides a sealer to be used for a bolt including a sprayed preservative coating coated onto at least a threaded portion. The sealer contains a wax therein in the range of 1 to 10 mass % both inclusive.Type: GrantFiled: December 17, 2012Date of Patent: February 3, 2015Assignees: Fuji Engineering Co., Ltd., Fujigiken Co., Ltd., West Nippon Expressway Company LimitedInventors: Masanobu Sugimoto, Yasuo Murayama, Kenichi Yamada, Yasutoshi Yamada
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Publication number: 20140293721Abstract: A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes.Type: ApplicationFiled: June 17, 2014Publication date: October 2, 2014Applicant: PS4 Luxco S.a.r.l.Inventors: Kazuhiko KAJIGAYA, Soichiro YOSHIDA, Yasutoshi YAMADA
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Publication number: 20140169911Abstract: The invention provides a sealer to be used for a bolt including a sprayed preservative coating coated onto at least a threaded portion. The sealer contains a wax therein in the range of 1 to 10 mass % both inclusive.Type: ApplicationFiled: December 17, 2012Publication date: June 19, 2014Applicants: FUJI ENGINEERING CO., LTD., WEST NIPPON EXPRESSWAY COMPANY LIMITED, FUJIGIKEN CO., LTD.Inventors: Masanobu SUGIMOTO, Yasuo MURAYAMA, Kenichi YAMADA, Yasutoshi YAMADA
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Publication number: 20140085997Abstract: A method includes accessing a memory cell to allow the memory cell to output data stored therein onto a local bit line; transferring, in response to a data read mode, a signal related to the data from the local bit line to a global bit line; and restoring, in response to a refresh mode, the data into the memory cell while keeping the local bit line electrically isolated from the global bit line.Type: ApplicationFiled: November 29, 2013Publication date: March 27, 2014Applicant: Elpida Memory, Inc.Inventors: Kazuhiko KAJIGAYA, Yasutoshi YAMADA
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Patent number: 8638630Abstract: A device includes a plurality of restoring circuits each provided for an associated one of local bit lines, remaining one or ones of the restoring circuits other than the restoring circuit provided for the selected one of the local bit lines being configured to receive, through remaining one or ones of the local bit lines, data that is or are read out from a memory cell or cells connected to the remaining one or ones of the local bit lines, and restore, through the remaining one or ones of the local bit lines, the data into the memory cell or cells connected to the remaining one or ones of the local bit lines.Type: GrantFiled: September 15, 2012Date of Patent: January 28, 2014Assignee: Elpida Memory, Inc.Inventors: Kazuhiko Kajigaya, Yasutoshi Yamada
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Patent number: 8605532Abstract: Disclosed herein is a semiconductor device comprising a memory cell, a local bit line coupled to the memory cell, a global bit line provided correspondingly to the local bit line, and a bit line control circuit coupled between the local bit line and the global bit line. The bit line control circuit includes a restoring circuit that is activated in a refresh mode to refresh data of the memory cell while being in electrical isolation from the global bit line.Type: GrantFiled: November 17, 2011Date of Patent: December 10, 2013Assignee: Elpida Memory, Inc.Inventors: Kazuhiko Kajigaya, Yasutoshi Yamada
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Publication number: 20130315018Abstract: A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes.Type: ApplicationFiled: November 13, 2012Publication date: November 28, 2013Applicant: ELPIDA MEMORY, INC.Inventors: Kazuhiko Kajigaya, Soichiro YOSHIDA, Yasutoshi YAMADA
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Patent number: 8587035Abstract: A device includes a semiconductor substrate, a first local bit line formed in the semiconductor substrate and elongated in a first direction, a first insulating layer on the semiconductor substrate, a first global bit line formed on the first insulating layer, a first path formed in the first insulating layer to couple a first end of the first local bit line with the first global bit line, and a second path formed in the first insulating layer to couple a second end of the first local bit line with the first global bit line.Type: GrantFiled: March 7, 2011Date of Patent: November 19, 2013Assignee: Elpida Memory, Inc.Inventors: Shinichi Takayama, Yasutoshi Yamada