Patents by Inventor Yasuyuki Baba
Yasuyuki Baba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230317173Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.Type: ApplicationFiled: May 31, 2023Publication date: October 5, 2023Inventors: Masanobu SHIRAKAWA, Takuya FUTATSUYAMA, Kenichi ABE, Hiroshi NAKAMURA, Keisuke YONEHAMA, Atsuhiro SATO, Hiroshi SHINOHARA, Yasuyuki BABA, Toshifumi MINAMI
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Patent number: 11705204Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.Type: GrantFiled: January 26, 2022Date of Patent: July 18, 2023Assignee: KIOXIA CORPORATIONInventors: Masanobu Shirakawa, Takuya Futatsuyama, Kenichi Abe, Hiroshi Nakamura, Keisuke Yonehama, Atsuhiro Sato, Hiroshi Shinohara, Yasuyuki Baba, Toshifumi Minami
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Publication number: 20230209829Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.Type: ApplicationFiled: March 1, 2023Publication date: June 29, 2023Inventors: Toshifumi MINAMI, Atsuhiro SATO, Keisuke YONEHAMA, Yasuyuki BABA, Hiroshi SHINOHARA, Hideyuki KAMATA, Teppei HIGASHITSUJI
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Patent number: 11621278Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.Type: GrantFiled: March 22, 2022Date of Patent: April 4, 2023Assignee: Kioxia CorporationInventors: Toshifumi Minami, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Hiroshi Shinohara, Hideyuki Kamata, Teppei Higashitsuji
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Publication number: 20220216232Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.Type: ApplicationFiled: March 22, 2022Publication date: July 7, 2022Inventors: Toshifumi MINAMI, Atsuhiro SATO, Keisuke YONEHAMA, Yasuyuki BABA, Hiroshi SHINOHARA, Hideyuki KAMATA, Teppei HIGASHITSUJI
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Publication number: 20220148657Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.Type: ApplicationFiled: January 26, 2022Publication date: May 12, 2022Inventors: Masanobu SHIRAKAWA, Takuya FUTATSUYAMA, Kenichi ABE, Hiroshi NAKAMURA, Keisuke YONEHAMA, Atsuhiro SATO, Hiroshi SHINOHARA, Yasuyuki BABA, Toshifumi MINAMI
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Patent number: 11315950Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.Type: GrantFiled: September 15, 2020Date of Patent: April 26, 2022Assignee: KIOXIA CORPORATIONInventors: Toshifumi Minami, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Hiroshi Shinohara, Hideyuki Kamata, Teppei Higashitsuji
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Patent number: 11270773Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.Type: GrantFiled: November 24, 2020Date of Patent: March 8, 2022Assignee: KIOXIA CORPORATIONInventors: Masanobu Shirakawa, Takuya Futatsuyama, Kenichi Abe, Hiroshi Nakamura, Keisuke Yonehama, Atsuhiro Sato, Hiroshi Shinohara, Yasuyuki Baba, Toshifumi Minami
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Publication number: 20210082519Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.Type: ApplicationFiled: November 24, 2020Publication date: March 18, 2021Inventors: Masanobu SHIRAKAWA, Takuya FUTATSUYAMA, Kenichi ABE, Hiroshi NAKAMURA, Keisuke YONEHAMA, Atsuhiro SATO, Hiroshi SHINOHARA, Yasuyuki BABA, Toshifumi MINAMI
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Publication number: 20200411551Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.Type: ApplicationFiled: September 15, 2020Publication date: December 31, 2020Inventors: Toshifumi MINAMI, Atsuhiro SATO, Keisuke YONEHAMA, Yasuyuki BABA, Hiroshi SHINOHARA, Hideyuki KAMATA, Teppei HIGASHITSUJI
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Patent number: 10854298Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.Type: GrantFiled: July 1, 2019Date of Patent: December 1, 2020Assignee: Toshiba Memory CorporationInventors: Masanobu Shirakawa, Takuya Futatsuyama, Kenichi Abe, Hiroshi Nakamura, Keisuke Yonehama, Atsuhiro Sato, Hiroshi Shinohara, Yasuyuki Baba, Toshifumi Minami
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Patent number: 10818691Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.Type: GrantFiled: September 13, 2019Date of Patent: October 27, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Toshifumi Minami, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Hiroshi Shinohara, Hideyuki Kamata, Teppei Higashitsuji
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Publication number: 20200006382Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.Type: ApplicationFiled: September 13, 2019Publication date: January 2, 2020Inventors: Toshifumi MINAMI, Atsuhiro SATO, Keisuke YONEHAMA, Yasuyuki BABA, Hiroshi SHINOHARA, Hideyuki KAMATA, Teppei HIGASHITSUJI
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Publication number: 20190348128Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.Type: ApplicationFiled: July 1, 2019Publication date: November 14, 2019Inventors: Masanobu SHIRAKAWA, Takuya FUTATSUYAMA, Kenichi ABE, Hiroshi NAKAMURA, Keisuke YONEHAMA, Atsuhiro SATO, Hiroshi SHINOHARA, Yasuyuki BABA, Toshifumi MINAMI
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Patent number: 10461093Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.Type: GrantFiled: February 12, 2018Date of Patent: October 29, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Toshifumi Minami, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Hiroshi Shinohara, Hideyuki Kamata, Teppei Higashitsuji
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Patent number: 10381084Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.Type: GrantFiled: August 7, 2018Date of Patent: August 13, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masanobu Shirakawa, Takuya Futatsuyama, Kenichi Abe, Hiroshi Nakamura, Keisuke Yonehama, Atsuhiro Sato, Hiroshi Shinohara, Yasuyuki Baba, Toshifumi Minami
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Publication number: 20180342300Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.Type: ApplicationFiled: August 7, 2018Publication date: November 29, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Masanobu SHIRAKAWA, Takuya FUTATSUYAMA, Kenichi ABE, Hiroshi NAKAMURA, Keisuke YONEHAMA, Atsuhiro SATO, Hiroshi SHINOHARA, Yasuyuki BABA, Toshifumi MINAMI
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Patent number: 10134749Abstract: A semiconductor memory device comprises a memory block including conductive layers at different levels from a substrate and separated from each other by a first insulation material. A memory pillar extends through the first conductive layers. A hookup region is adjacent to the memory block and includes conductive layers stacked on the substrate at levels from the substrate that corresponds to the conductive layers in the memory block. An isolation region is between the memory block and the hookup region and includes first insulating layers of a second insulating material different than the first insulating material. Each first insulating layer is at a level from the substrate that corresponds to one of the first conductive layers and each first insulating layer is between one of the conductive layers in the memory block and one of the conductive layers in hookup region.Type: GrantFiled: April 18, 2017Date of Patent: November 20, 2018Assignee: Toshiba Memory CorporationInventors: Mitsuhiro Noguchi, Yoshitaka Kubota, Yasuyuki Baba
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Patent number: 10074434Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.Type: GrantFiled: October 23, 2017Date of Patent: September 11, 2018Assignee: Toshiba Memory CorporationInventors: Masanobu Shirakawa, Takuya Futatsuyama, Kenichi Abe, Hiroshi Nakamura, Keisuke Yonehama, Atsuhiro Sato, Hiroshi Shinohara, Yasuyuki Baba, Toshifumi Minami
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Patent number: 10020319Abstract: A semiconductor memory device includes a plurality of wiring layers formed on a substrate, one or more first pillars penetrating through the wiring layers on a memory region of the substrate and in contact with the substrate, a plurality of memory transistors being formed at portions of each of the one or more first pillars that penetrate the wiring layers, and one or more second pillars penetrating through at least one of the wiring layers on a peripheral region of the substrate and in contact with the substrate. Each of the first and second pillars includes a semiconductor portion, a first insulating layer formed around the semiconductor portion, a charge accumulation layer formed around the first insulating layer, and a second insulating layer formed around the charge accumulation layer.Type: GrantFiled: August 10, 2016Date of Patent: July 10, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventor: Yasuyuki Baba