Patents by Inventor Yasuyuki Matsuoka
Yasuyuki Matsuoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090108333Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a first columnar semiconductor layer extending in a direction perpendicular to a substrate; a charge accumulation layer formed on the first columnar semiconductor layer via a first air gap and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of first conductive layers contacting the block insulation layer.Type: ApplicationFiled: October 29, 2008Publication date: April 30, 2009Applicant: Kabushiki Kasiha ToshibaInventors: Masaru KITO, Ryota KATSUMATA, Masaru KIDOH, Hiroyasu TANAKA, Yoshiaki FUKUZUMI, Hideaki AOCHI, Yasuyuki MATSUOKA
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Publication number: 20090101969Abstract: A semiconductor device comprising: a semiconductor substrate; a first conductive layer provided on a surface of the substrate and serving as one of a source and a drain; a first insulating film provided on the first conductive layer; a gate electrode film provided on the first insulating film; a second insulating film provided on the gate electrode film; a gate opening provided so as to penetrate the second insulating film, the gate electrode film and the first insulating film to expose a part of the first conductive layer; a recess provided in the surface of the first conductive layer just below the gate opening; a gate insulator provided on the side surface of the gate opening and having a projecting shape at a portion between the first insulating film and the recess; a second conductive layer buried in the recess and in a bottom of the gate opening so as to be in contact with the gate insulator, and serving as the one of the source and the drain while being in contact with the first conductive layer; a chaType: ApplicationFiled: October 9, 2008Publication date: April 23, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Ryota KATSUMATA, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Hideaki Aochi, Yasuyuki Matsuoka
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Publication number: 20090090965Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a memory columnar semiconductor extending in a direction perpendicular to a substrate; a tunnel insulation layer contacting the memory columnar semiconductor; a charge accumulation layer contacting the tunnel insulation layer and accumulating charges; a block insulation layer contacting the charge accumulation layer; and a plurality of memory conductive layers contacting the block insulation layer. The lower portion of the charge accumulation layer is covered by the tunnel insulation layer and the block insulation layer.Type: ApplicationFiled: October 3, 2008Publication date: April 9, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masaru KITO, Ryota Katsumata, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Hideaki Aochi, Yasuyuki Matsuoka
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Publication number: 20090001444Abstract: This disclosure concerns a semiconductor memory device comprising a plurality of gate electrodes extending to a first direction; a reinforced insulation film extending to a second direction crossing the first direction, and connected to the adjacent gate electrodes; and an interlayer dielectric film provided between the adjacent gate electrodes, and having a void inside.Type: ApplicationFiled: June 3, 2008Publication date: January 1, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yasuyuki MATSUOKA, Masaru Kito, Hideaki Aochi, Takayuki Okamura
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Publication number: 20080315291Abstract: A nonvolatile semiconductor memory device has a plurality of memory strings each including a plurality of electrically rewritable memory cells serially connected. The memory string includes a columnar semiconductor portion extending in the vertical direction from a substrate, a first charge storage layer formed adjacent to the columnar semiconductor portion and configured to accumulate charge, a first block insulator formed adjacent to the first charge storage layer, and a first conductor formed adjacent to the first block insulator.Type: ApplicationFiled: June 17, 2008Publication date: December 25, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masaru KITO, Hideaki Aochi, Ryota Katsumata, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka
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Publication number: 20080315296Abstract: A non-volatile semiconductor storage device 10 has a plurality of memory strings 100 with a plurality of electrically rewritable memory transistors MTr1-MTr4 connected in series. The memory string 100 includes a columnar semiconductor CLmn extending in a direction perpendicular to a substrate, a plurality of charge accumulation layers formed around the columnar semiconductor CLmn via insulating films, and selection gate lines on the drain side SGD contacting the columnar semiconductor to configure transistors. The selection gate lines on the drain side SGD have lower selection gate lines on the drain side SGDd, each of which is arranged with an interval with a certain pitch, and upper selection gate lines on the drain side SGDu located on a higher layer than the lower selection gate lines on the drain side SGDd, each of which is arranged on gaps between the lower selection gate lines on the drain side SGDd.Type: ApplicationFiled: June 19, 2008Publication date: December 25, 2008Applicant: Kabushiki Kaisha ToshibaInventors: Hiroyasu TANAKA, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kido, Hideaki Aochi, Mitsuru Sato, Yasuyuki Matsuoka
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Publication number: 20080180994Abstract: A semiconductor memory device has a semiconductor substrate, first select transistors formed on the surface of said semiconductor substrate, first dummy transistors formed above said first select transistors, a plurality of memory cell transistors formed above said first dummy transistors so as to extend in a direction perpendicular to the surface of said semiconductor substrate, each of said memory cell transistor including an insulating layer having a charge-accumulating function, second dummy transistors formed above said memory cell transistors, and second select transistors formed above said second dummy transistors; wherein a first potential is provided to the gate electrodes of said first select transistors and the gate electrodes of said first dummy transistors and a second potential is provided to the gate electrodes of said second select transistors and the gate electrodes of said second dummy transistors at the time of write operation to write data to said memory cell transistors.Type: ApplicationFiled: December 13, 2007Publication date: July 31, 2008Applicant: KABUSHIKI KAISHA TOSHIBIAInventors: Ryota Katsumata, Masaru Kidoh, Hiroyasu Tanaka, Masaru Kito, Hideaki Aochi, Yoshiaki Fukuzumi, Yasuyuki Matsuoka
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Publication number: 20080173932Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory including: a columnar semiconductor; a charge storage insulating film including: a first insulating film formed around the columnar semiconductor, a charge storage film formed around the first insulating film, and a second insulating film formed around the charge storage film; an electrode extending two-dimensionally to surround the charge storage insulating film, the electrode having a groove; and a metal silicide formed on a sidewall of the groove.Type: ApplicationFiled: January 8, 2008Publication date: July 24, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masaru KIDOH, Ryota KATSUMATA, Masaru KITO, Yoshiaki FUKUZUMI, Hideaki AOCHI, Hiroyasu TANAKA, Yasuyuki MATSUOKA, Yoshio OZAWA, Mitsuru SATO
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Publication number: 20070252201Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.Type: ApplicationFiled: January 18, 2007Publication date: November 1, 2007Inventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
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Patent number: 6936774Abstract: A transfer material capable of transferring a fine wiring pattern to a substrate reliably and easily. The transfer material includes at least three layers of a first metal layer as a carrier, a second metal layer that is transferred to the substrate as a wiring pattern, and a peel layer adhering the first and second metal layers releasably. On the surface portion of the first metal layer, a concave and convex portion corresponding to the wiring pattern is formed, and the peel layer and the second metal layer are formed on a region of the convex portions.Type: GrantFiled: October 29, 2002Date of Patent: August 30, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yasuhiro Sugaya, Shingo Komatsu, Koichi Hirano, Seiichi Nakatani, Yasuyuki Matsuoka, Toshiyuki Asahi, Yoshihisa Yamashita
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Publication number: 20050186768Abstract: A transfer material capable of transferring a fine wiring pattern to a substrate reliably and easily. The transfer material includes at least three layers of a first metal layer as a carrier, a second metal layer that is transferred to the substrate as a wiring pattern, and a peel layer adhering the first and second metal layers releasably. On the surface portion of the first metal layer, a concave and convex portion corresponding to the wiring pattern is formed, and the peel layer and the second metal layer are formed on a region of the convex portions.Type: ApplicationFiled: March 25, 2005Publication date: August 25, 2005Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Yasuhiro Sugaya, Shingo Komatsu, Koichi Hirano, Seiichi Nakatani, Yasuyuki Matsuoka, Toshiyuki Asahi, Yoshihisa Yamashita
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Patent number: 6931725Abstract: A circuit component built-in module capable of mounting the circuit component with high density and having high heat releasing property and the high reliability. The circuit component built-in module 100 includes the insulating substrate 101 made of a first mixture 105 and a second mixture 106, wiring patterns 102a and 102b formed on one principal surface and another principal surface of the insulating substrate 101, a circuit component 103a electrically connected to the wiring pattern 102a and sealed with the second mixture 106 in an internal portion of the insulating substrate 101, the inner via conductor 104 electrically connecting the wiring pattern 102a and 102b.Type: GrantFiled: January 9, 2003Date of Patent: August 23, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yasuhiro Sugaya, Koichi Hirano, Seiichi Nakatani, Yasuyuki Matsuoka, Satoru Yuuhaku, Toshiyuki Asahi
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Patent number: 6871396Abstract: A transfer material capable of transferring a fine wiring pattern to a substrate reliably and easily. The transfer material includes at least three layers of a first metal layer as a carrier, a second metal layer that is transferred to the substrate as a wiring pattern, and a peel layer adhering the first and second metal layers releasably. On the surface portion of the first metal layer, a concave and convex portion corresponding to the wiring pattern is formed, and the peel layer and the second metal layer are formed on a region of the convex portions.Type: GrantFiled: February 7, 2001Date of Patent: March 29, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yasuhiro Sugaya, Shingo Komatsu, Koichi Hirano, Seiichi Nakatani, Yasuyuki Matsuoka, Toshiyuki Asahi, Yoshihisa Yamashita
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Publication number: 20030141105Abstract: A circuit component built-in module capable of mounting the circuit component with high density and having high heat releasing property and the high reliability. The circuit component built-in module 100 includes the insulating substrate 101 made of a first mixture 105 and a second mixture 106, wiring patterns 102a and 102b formed on one principal surface and another principal surface of the insulating substrate 101, a circuit component 103a electrically connected to the wiring pattern 102a and sealed with the second mixture 106 in an internal portion of the insulating substrate 101, the inner via conductor 104 electrically connecting the wiring pattern 102a and 102b.Type: ApplicationFiled: January 9, 2003Publication date: July 31, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Yasuhiro Sugaya, Koichi Hirano, Seiichi Nakatani, Yasuyuki Matsuoka, Satoru Yuuhaku, Toshiyuki Asahi
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Publication number: 20030102153Abstract: A transfer material capable of transferring a fine wiring pattern to a substrate reliably and easily. The transfer material includes at least three layers of a first metal layer as a carrier, a second metal layer that is transferred to the substrate as a wiring pattern, and a peel layer adhering the first and second metal layers releasably. On the surface portion of the first metal layer, a concave and convex portion corresponding to the wiring pattern is formed, and the peel layer and the second metal layer are formed on a region of the convex portions.Type: ApplicationFiled: October 29, 2002Publication date: June 5, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Yasuhiro Sugaya, Shingo Komatsu, Koichi Hirano, Seiichi Nakatani, Yasuyuki Matsuoka, Toshiyuki Asahi, Yoshihisa Yamashita
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Patent number: 6538210Abstract: A circuit component built-in module capable of mounting the circuit component with high density and having high heat releasing property and the high reliability. The circuit component built-in module 100 includes the insulating substrate 101 made of a first mixture 105 and a second mixture 106, wiring patterns 102a and 102b formed on one principal surface and another principal surface of the insulating substrate 101, a circuit component 103a electrically connected to the wiring pattern 102a and sealed with the second mixture 106 in an internal portion of the insulating substrate 101, the inner via conductor 104 electrically connecting the wiring pattern 102a and 102b.Type: GrantFiled: December 15, 2000Date of Patent: March 25, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yasuhiro Sugaya, Koichi Hirano, Seiichi Nakatani, Yasuyuki Matsuoka, Satoru Yuuhaku, Toshiyuki Asahi
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Publication number: 20010030059Abstract: A circuit component built-in module capable of mounting the circuit component with high density and having high heat releasing property and the high reliability. The circuit component built-in module 100 includes the insulating substrate 101 made of a first mixture 105 and a second mixture 106, wiring patterns 102a and 102b formed on one principal surface and another principal surface of the insulating substrate 101, a circuit component 103a electrically connected to the wiring pattern 102a and sealed with the second mixture 106 in an internal portion of the insulating substrate 101, the inner via conductor 104 electrically connecting the wiring pattern 102a and 102b.Type: ApplicationFiled: December 15, 2000Publication date: October 18, 2001Inventors: Yasuhiro Sugaya, Koichi Hirano, Seiichi Nakatani, Yasuyuki Matsuoka, Satoru Yuuhaku, Toshiyuki Asahi
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Publication number: 20010023779Abstract: A transfer material capable of transferring a fine wiring pattern to a substrate reliably and easily. The transfer material includes at least three layers of a first metal layer as a carrier, a second metal layer that is transferred to the substrate as a wiring pattern, and a peel layer adhering the first and second metal layers releasably. On the surface portion of the first metal layer, a concave and convex portion corresponding to the wiring pattern is formed, and the peel layer and the second metal layer are formed on a region of the convex portions.Type: ApplicationFiled: February 7, 2001Publication date: September 27, 2001Inventors: Yasuhiro Sugaya, Shingo Komatsu, Koichi Hirano, Seiichi Nakatani, Yasuyuki Matsuoka, Toshiyuki Asahi, Yoshihisa Yamashita
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Patent number: 6095203Abstract: A method for injecting a liquid crystal material into a liquid crystal panel which is provided with a liquid crystal injection port and an evacuation port is provided. The method includes the steps of: evacuating the liquid crystal panel; and after the evacuation step, injecting the liquid crystal material into the liquid crystal panel through the liquid crystal injection port with the liquid crystal material being pressurized while evacuating the liquid crystal panel.Type: GrantFiled: September 11, 1997Date of Patent: August 1, 2000Assignee: Sharp Kabushiki KaishaInventors: Yuichi Yamamoto, Akira Ohnishi, Yasuyuki Matsuoka, Masaru Yamaguchi