Patents by Inventor Yasuyuki Matsuya

Yasuyuki Matsuya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11196441
    Abstract: A sensor device includes an A/D converter including an adder that computes a difference between an analog input signal and a predicted value, the adder includes a capacitive adder defined by a series circuit including a capacitive charge output device and a capacitor. A capacitive component in the charge output device defines a portion of the capacitance of the capacitive adder. A digital prediction filter generates the predicted value based on an output from a quantizer. The capacitive adder computes the difference between the analog input signal from the charge output device and the predicted value. The quantizer quantizes and encodes the difference. The A/D converter performs a ? modulation on the analog input signal which is converted into a digital signal.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: December 7, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasuhide Takase, Yasuyuki Matsuya
  • Patent number: 10523227
    Abstract: An A/D converter includes an adder that calculates a difference between an analog input signal and a predicted value, a quantizer that quantizes the difference output from the adder to convert the analog input signal to a digital signal, a prediction filter that generates a predicted value from the digital signal output from the quantizer, and a D/A converter that converts the predicted value from a digital signal to an analog signal and output the predicted value to the adder. The predicted value before being subjected to conversion to the analog signal by the D/A converter defines and functions as an A/D converted output of the analog input signal input to the adder.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: December 31, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasuhide Takase, Yasuyuki Matsuya, Eri Mizukami, Yuji Inagaki, Kazuki Mizukami, Nozomi Watanabe, Riku Yonekawa
  • Publication number: 20190044527
    Abstract: An A/D converter includes an adder that calculates a difference between an analog input signal and a predicted value, a quantizer that quantizes the difference output from the adder to convert the analog input signal to a digital signal, a prediction filter that generates a predicted value from the digital signal output from the quantizer, and a D/A converter that converts the predicted value from a digital signal to an analog signal and output the predicted value to the adder. The predicted value before being subjected to conversion to the analog signal by the D/A converter defines and functions as an A/D converted output of the analog input signal input to the adder.
    Type: Application
    Filed: October 12, 2018
    Publication date: February 7, 2019
    Inventors: Yasuhide TAKASE, Yasuyuki MATSUYA, Eri Mizukami, Yuji INAGAKI, Kazuki Mizukami, Nozomi WATANABE, Riku YONEKAWA
  • Publication number: 20180262204
    Abstract: A sensor device includes an A/D converter including an adder that computes a difference between an analog input signal and a predicted value, the adder includes a capacitive adder defined by a series circuit including a capacitive charge output device and a capacitor. A capacitive component in the charge output device defines a portion of the capacitance of the capacitive adder. A digital prediction filter generates the predicted value based on an output from a quantizer. The capacitive adder computes the difference between the analog input signal from the charge output device and the predicted value. The quantizer quantizes and encodes the difference. The A/D converter performs a ? modulation on the analog input signal which is converted into a digital signal.
    Type: Application
    Filed: May 15, 2018
    Publication date: September 13, 2018
    Inventors: Yasuhide TAKASE, Yasuyuki MATSUYA
  • Patent number: 8731006
    Abstract: When a data signal of a first channel is an RZ signal having a pulse period T1 and a logic “1” pulse width m, a data signal of a second channel is an RZ signal having a pulse period T2 and a logic “1” pulse width n and the relation n<m is satisfied, a multiplexed signal D obtained by time-division multiplexing the data signals of two channels is input. A pulse signal with a pulse width k satisfying n<k<min(m, T2) is generated at timing of a leading edge of the data signal of each channel. When the multiplexed signal D is judged as logic “1” at timing of a trailing edge of the pulse signal, the data signal of the first channel is output. Similarly, when the multiplexed signal D is judged as logic “0”, the data signal of the second channel is output.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: May 20, 2014
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Yasuyuki Matsuya, Takako Ishihara, Shinichiro Mutoh, Sadayuki Yasuda
  • Publication number: 20110170636
    Abstract: When a data signal of a first channel is an RZ signal having a pulse period T1 and a logic “1” pulse width m, a data signal of a second channel is an RZ signal having a pulse period T2 and a logic “1” pulse width n and the relation n<m is satisfied, a multiplexed signal D obtained by time-division multiplexing the data signals of two channels is input. A pulse signal with a pulse width k satisfying n<k<min(m, T2) is generated at timing of a leading edge of the data signal of each channel. When the multiplexed signal D is judged as logic “1” at timing of a trailing edge of the pulse signal, the data signal of the first channel is output. Similarly, when the multiplexed signal D is judged as logic “0”, the data signal of the second channel is output.
    Type: Application
    Filed: January 12, 2011
    Publication date: July 14, 2011
    Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Yasuyuki Matsuya, Takako Ishihara, Shinichiro Mutoh, Sadayuki Yasuda
  • Patent number: 7894490
    Abstract: When a data signal of a first channel is an RZ signal having a pulse period T1 and a logic “1” pulse width m, a data signal of a second channel is an RZ signal having a pulse period T2 and a logic “1” pulse width n and the relation n < m is satisfied, a multiplexed signal D obtained by time-division multiplexing the data signals of two channels is input. A pulse signal with a pulse width k satisfying n < k < min(m, T2) is generated at timing of a leading edge of the data signal of each channel. When the multiplexed signal D is judged as logic “1” at timing of a trailing edge of the pulse signal, the data signal of the first channel is output. Similarly, when the multiplexed signal D is judged as logic “0”, the data signal of the second channel is output.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: February 22, 2011
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Yasuyuki Matsuya, Takako Ishihara, Shinichiro Mutoh, Sadayuki Yasuda
  • Publication number: 20090175300
    Abstract: When a data signal of a first channel is an RZ signal having a pulse period T1 and a logic “1” pulse width m, a data signal of a second channel is an RZ signal having a pulse period T2 and a logic “1” pulse width n and the relation n<m is satisfied, a multiplexed signal D obtained by time-division multiplexing the data signals of two channels is input. A pulse signal with a pulse width k satisfying n<k<min(m, T2) is generated at timing of a leading edge of the data signal of each channel. When the multiplexed signal D is judged as logic “1” at timing of a trailing edge of the pulse signal, the data signal of the first channel is output. Similarly, when the multiplexed signal D is judged as logic “O”, the data signal of the second channel is output.
    Type: Application
    Filed: December 7, 2006
    Publication date: July 9, 2009
    Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Yasuyuki Matsuya, Takako Ishihara, Shinichiro Mutoh, Sadayuki Yasuda
  • Publication number: 20070127604
    Abstract: A receiving section of an infrared receiver includes an error detecting section that detects, through an integrating circuit, a direct-current component of a 1-bit data sequence that is supplied in a form of a PDM signal. The direct-current component thus detected is compared with a reference voltage by the comparing circuit to determine whether the direct-current component is greater or smaller than the reference voltage, and a signal is outputted on the basis of a result of the comparison. When the direct-current component is decreased, it is determined that a bit error rate is greater. At this time, an output of sound from the infrared receiver is caused to become OFF.
    Type: Application
    Filed: November 22, 2006
    Publication date: June 7, 2007
    Inventors: Takahiro Inoue, Yasuyuki Matsuya, Takako Ishihara
  • Publication number: 20040062362
    Abstract: A data communication method, a data transmitting apparatus, a data receiving apparatus, and a data transmission program are provided which do not cause the problem of jitter being generated by a combination of a 1-bit noise shaping A/D converter and on-off keying using infrared rays. In a data transmitting apparatus, analog signals comprising voice or music or signals obtained by digitizing these are converted using a noise shaping method into non-return-to-zero digital signals formed by 1-bit data streams. For converted digital signals of “1”, return-to-zero signals having a pulse width smaller than that of non-return-to-zero signals and that have been allocated a high level are converted into radio signals and transmitted. For converted digital signals of “0”, return-to-zero signals allocated a low level are converted into radio signals and transmitted. A data receiving apparatus receives these radio signals and drives a musical sound output section to output musical sound signals.
    Type: Application
    Filed: September 16, 2003
    Publication date: April 1, 2004
    Inventor: Yasuyuki Matsuya
  • Patent number: 6191624
    Abstract: In a voltage comparator, a positive feedback circuit having first and second inverters compares the potential of the input terminal of the first inverter with the potential of the input terminal of the second inverter and outputs the comparison result from the output terminal of the second inverter. A first input circuit supplies the first potential corresponding to an input comparison voltage to the input terminal of the second inverter. A second input circuit supplies the second potential corresponding to an input reference voltage to the input terminal of the first inverter. A control circuit supplies a power supply voltage to the positive feedback circuit when an input control signal represents a comparison operation period to execute voltage comparison operation. When the control signal represents an initialization period, the control circuit stops supplying the power supply voltage to set an initial state.
    Type: Grant
    Filed: October 25, 1999
    Date of Patent: February 20, 2001
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventor: Yasuyuki Matsuya
  • Patent number: 5486774
    Abstract: A logic circuit includes a low-threshold logic circuit, a pair of first and second power lines, a first dummy power line, and a first high-frequency logic circuit. The low-threshold logic circuit has a logic circuit element constituted by a plurality of low-threshold field effect transistors. The pair of first and second power lines supply power to the low-threshold logic circuit. The first dummy power line is connected to one of power source terminals of the low-threshold logic circuit. The first high-threshold control transistor is arranged between the first dummy power line and the first power line.
    Type: Grant
    Filed: November 2, 1994
    Date of Patent: January 23, 1996
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Takakuni Douseki, Junzo Yamada, Yasuyuki Matsuya, Shinichirou Mutou
  • Patent number: 5473571
    Abstract: A data hold circuit storing a logic state of a predetermined node of a logic circuit immediately before power supply to the logic circuit is interrupted, and restoring the stored logic state to the predetermined node immediately after the power supply is restarted. The data hold circuit includes a memory circuit storing the logic state of the node, a switch circuit connected between the memory circuit and the node, and a control circuit controlling the on/off operation of the switch circuit. The control circuit turns on the switch circuit for a predetermined time period when the power supply is changed from on to off, or from off to on. The memory circuit is continuously supplied with power from a power supply other than that for the logic circuit. While the power supply to the logic circuit is in a steady state either in the power on state or power off state, the switch circuit is kept off, thereby preventing effect of the memory circuit on the logic circuit.
    Type: Grant
    Filed: September 29, 1994
    Date of Patent: December 5, 1995
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Satoshi Shigematsu, Shin'ichiro Mutoh, Yasuyuki Matsuya
  • Patent number: 5416483
    Abstract: A noise shaping circuit permitting a wide dynamic range for input signal and having an improved S/N ratio. In FIG. 1, the circuit comprises a delay part 3 for delaying the output signal for a one-sampling period; a first subtraction part 1 for subtracting the delayed signal, via the delay part 3 from the input signal imparted to the input terminal so as to generate first subtraction results; a first integration part 2 for integrating the first subtraction results; a second subtraction part 4 for subtracting the input signal from the first integrated value of the part 2; a second integration part 5 for integrating the second subtraction value so as to obtain a second integrated value; an addition part 7 for adding the first and second integrated values so as to obtain an addition results, and a quantizer 6 for quantizing the addition results. The amplitude of the signal imparted to the part 5 is minimized by means of the part 4, so that the dynamic range of the part 5 is utilized with high efficiency.
    Type: Grant
    Filed: December 11, 1992
    Date of Patent: May 16, 1995
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventor: Yasuyuki Matsuya
  • Patent number: 4415882
    Abstract: The analog output from a local DAC comprising an LDAC and an MDAC, in which the full scale of the LDAC is always larger than the quantized level of the MDAC, is compared with an input analog signal which is sampled and held. A digital code obtained by successive approximation in accordance with the result of the comparison is stored in a successive approximation register. A shift code for calibrating the D/A conversion in the local DAC by shifting the digital code which is previously allotted to each digital code is stored in a shift code generating circuit (ROM). The digital code from the successive approximation register is digitally shifted in accordance with the shift code by a code shift circuit such as a digital adder/subtractor to obtain an A/D conversion output. An analog to digital converter with a high accuracy and an improved conversion speed is inexpensively fabricated in the form of a one chip LSI by a usual CMOS process.
    Type: Grant
    Filed: September 3, 1981
    Date of Patent: November 15, 1983
    Assignee: Nippon Telegraph & Telephone Public Corporation
    Inventors: Yukio Akazawa, Yasuyuki Matsuya, Atsushi Iwata
  • Patent number: 4412208
    Abstract: A digital to analog converter comprising a first digital to analog converter for generating an output signal of higher order bits; a second digital to analog converter for generating a full scale output as an output signal of lower order bits which is always larger than the output value (1 LSB) corresponding to one bit of a digital input at the least significant bit of the first digital to analog converter; adding means for adding the output signal from the first digital to analog converter to the output signal from the second digital to analog converter to form an analog output signal; and a code converter for applying to the first and second digital to analog converters an input code obtained by shifting a digital input signal applied to the first and second digital to analog converters by a given value such that the relationship between the digital input signal and the analog output signal is made substantially linear.
    Type: Grant
    Filed: September 3, 1981
    Date of Patent: October 25, 1983
    Assignee: Nippon Telegraph & Telephone Public Corporation
    Inventors: Yukio Akazawa, Yasuyuki Matsuya, Atsushi Iwata