Abstract: This semiconductor device (100A) includes: an oxide layer (15) which includes a semiconductor region (5) and a conductor region (7) that contacts with the semiconductor region; a source electrode (6s) and a drain electrode (6d) which are electrically connected to the semiconductor region; an insulating layer (11) formed on the source and drain electrodes; a transparent electrode (9) arranged to overlap at least partially with the conductor region with the insulating layer interposed between them; a source line (6a) formed out of the same conductive film as the source electrode; and a gate extended line (3a) formed out of the same conductive film as a gate electrode (3). The source line is electrically connected to the gate extended line via a transparent connecting layer (9a) which is formed out of the same conductive film as the transparent electrode.

Abstract: The TFT substrate (10) of this liquid crystal display device (100) includes: a TFT (11) which is provided for each pixel; an upper electrode (12) which is electrically connected to the TFT's drain electrode (11d); a lower electrode (13) which is arranged under the upper electrode; and a dielectric layer (14) which is arranged between the upper and lower electrodes. Its counter substrate (20) includes a counter electrode (21) which faces the upper electrode. The upper electrode has first and second regions (R1, R2) which have mutually different electrode structures, and a third region (R3) which electrically connects the first and second regions to the drain electrode. The third region of the upper electrode includes a symmetrical connecting portion (12c) that is a conductive film pattern, of which the shape is substantially symmetrical with respect to a virtual line (L1) that splits each pixel into two adjacent regions in a row direction.

Abstract: Provided is a liquid crystal display device with reduced power consumption employing a CS drive method. A CS driver (500) consists of a CS shift register (510) and a CS output portion (520). The CS shift register (510) outputs control signals (COUT(1) to COUT(m)) in accordance with a CS clock signal CCK. The CS output portion (520) outputs auxiliary capacitance signals (CSS(1) to CSS(m)) in accordance with the control signals (COUT(1) to COUT(m)), respectively. An idle period (T2) is set following a scanning period (T1). During the idle period (T2), the CS driver (500) is driven in accordance with the CS clock signal (CCK) at an idle-period CS frequency (fcck2). The idle-period CS frequency (fcck2) is lower than a scanning-period CS frequency (fcck1).

Abstract: This semiconductor device (100) includes: a gate electrode (3); a gate insulating layer (4); an oxide layer (50) which is formed on the gate insulating layer (4) and which includes a first conductor region (55) and a first semiconductor region (51) that overlaps at least partially with the gate electrode (3) with the gate insulating layer (4) interposed between them; a source electrode (6s) formed to contact with the upper surface of the first semiconductor region (51) of the oxide layer (50); a drain electrode (6d) which is formed to contact with the upper surface of the first semiconductor region (51) of the oxide layer (50) and which is electrically connected to the first conductor region (55); and a conductive layer (60) which is formed in contact with the upper surface of the oxide layer (50) and which a plurality of holes (66) or notches.

Abstract: A shift register 10 is configured such that m unit circuits 11 each including a shift unit 12 and three buffer units 13r, 13g, and 13b are in a multi-stage cascade connection and that 3m signals in total including three signals from each stage are outputted. The m shift units 12 perform a shift operation, and a first signal Y is outputted from each stage. When a clock signal CK is at a high level, the first signal Y rises higher than a normal high level due to bootstrapping. The buffer unit 13r controls an output signal YR to be at a high level based on the buffer control signal CR and the first signal Y. A buffer control circuit 7 controls buffer control signals CR, CG, and CB to be at a high level for a time period shorter than a half cycle of the clock signal. With this, a shift register with a reduced circuit amount and low power consumption is provided.

Abstract: A semiconductor layer for an active element included in each of a plurality of pixels in a display section is constituted by an oxide layer containing at least one element selected from the group consisting of In, Ga, and Zn. There is provided, for the display section, a liquid crystal panel's timing controller (13) configured to carry out control so that (i) a length of a first period during which image data is written is not more than twice that of the second period and/or (ii) one (1) frame period is longer than 16.7 msec.

Abstract: A display device includes: a display unit, a driver unit, and a control unit. The display unit includes a plurality of pixel units arranged in a matrix. The driver unit includes an output transistor configured to drive a plurality of scanning lines connected to the plurality of pixel units. The control unit is configured to supply to the driver unit in a display period, a signal for displaying an image on the display unit, and control a bias state of the output transistor in a display suspension period, so that an absolute value of a threshold voltage of the output transistor which is increased in the display period decreases.

Abstract: This TFT substrate (100A) includes: a gate connecting layer (3a) formed on a substrate (1) out of a same conductive film as a gate electrode (3) or a transparent connecting layer (2a) formed on the substrate (1) out of a same conductive film as a first transparent electrode (2); an oxide layer (5z) which is formed on an insulating layer (4) and which includes at least one conductor region (5a); and a source connecting layer (6a) formed on the oxide layer (5z) out of a same conductor film as a source electrode (6s). The source connecting layer (6a) is electrically connected to either the gate connecting layer (3a) or the transparent connecting layer (2a) via the at least one conductor region (5a).

Abstract: This semiconductor device (100A) includes: a substrate (1); a gate electrode (3) and a first transparent electrode (2) which are formed on the substrate (1); a first insulating layer (4) formed over the gate electrode (3) and the first transparent electrode (2); an oxide semiconductor layer (5) formed on the first insulating layer (4); source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5); and a second transparent electrode (7) electrically connected to the drain electrode (6d). At least a portion of the first transparent electrode (2) overlaps with the second transparent electrode (7) with the first insulating layer (4) interposed between them, and the oxide semiconductor layer (5) and the second transparent electrode (7) are formed out of the same oxide film.

Abstract: It is an object of the present invention to provide a medicament for preventing or treating hyperphosphatemia. Solution: A compound represented by a general formula (I) or a pharmacologically acceptable salt thereof. [In the formula, R1: a methyl group or the like, R2: a hydrogen atom or the like, R3: a hydrogen atom or the like, A: a cyclohexyl ring or the like, X: CH or the like, Y: CH or the like, Z: CH or the like, and n: 2 or the like.

Abstract: In order to suppress crosstalk between a pixel electrode and a source line to reduce flicker, an LCD device includes: gate lines 102 and source lines 105 which are provided in a grid pattern; pixel electrodes 111 arranged in a matrix pattern so as to correspond to intersections of the gate lines and the source lines; a transparent auxiliary capacitor electrode 109; and switching elements 121 configured to apply an image signal voltage supplied from the source line 105 to the pixel electrode 111 according to a scanning signal applied from the gate line 102. The switching element 121 is formed by using an oxide semiconductor layer 104, and the transparent auxiliary capacitor electrode 109 is provided between the source line 105 and the pixel electrode 111.

Abstract: A shift register circuit has a plurality of unit circuits that are cascade-connected to one another and that output received pulse signals as output signals in accordance with a clock signal, the shift register circuit sequentially outputting the output signals from the plurality of respective unit circuits. The output circuits each include a double-gate transistor having first gate electrode that controls conductivity between the drain electrode and the source electrode, and a second gate electrode formed through an insulating layer and disposed to face the first gate electrode across a semiconductor layer between the drain electrode and the source electrode. The shift register circuit applies a prescribed voltage to the second gate electrode in accordance with a voltage applied to the first gate electrode.

Abstract: This semiconductor device (100A) includes: a substrate (2); a gate electrode (3) formed on the substrate (2); a gate insulating layer (4) formed over the gate electrode (3); an oxide semiconductor layer (5) formed on the gate insulating layer (4); source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5); a first transparent electrode (7) electrically connected to the drain electrode (6d); an interlayer insulating layer (8) including a dielectric layer (8a) formed over the source and drain electrodes (6s, 6d); and a second transparent electrode (9) formed on the interlayer insulating layer (8). At least a portion of the second transparent electrode (9) overlaps with the first transparent electrode (7) with the dielectric layer (8a) interposed between them, and the oxide semiconductor layer (5) and the first transparent electrode (7) are formed out of the same oxide film.

Abstract: This TFT substrate (100A) includes: a gate connecting layer (3a) formed on a substrate (1) out of a same conductive film as a gate electrode (3) or a transparent connecting layer (2a) formed on the substrate (1) out of a same conductive film as a first transparent electrode (2); an oxide layer (5z) which is formed on an insulating layer (4) and which includes at least one conductor region (5a); and a source connecting layer (6a) formed on the oxide layer (5z) out of a same conductor film as a source electrode (6s). The source connecting layer (6a) is electrically connected to either the gate connecting layer (3a) or the transparent connecting layer (2a) via the at least one conductor region (5a).

Abstract: This semiconductor device (100A) includes: a substrate (2); a gate electrode (3) formed on the substrate (2); a gate insulating layer (4) formed over the gate electrode (3); an oxide semiconductor layer (5) formed on the gate insulating layer (4); source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5); a first transparent electrode (7) electrically connected to the drain electrode (6d); an interlayer insulating layer (8a) including portions formed on the source and drain electrodes (6s, 6d); and a second transparent electrode (9) formed on the interlayer insulating layer (8a). At least a portion of the second transparent electrode (9) overlaps with the first transparent electrode (7) with the interlayer insulating layer (8a) interposed between them. And the oxide semiconductor layer (5) and the first transparent electrode (7) are formed out of a same oxide film.

Abstract: A TFT substrate (100A) includes an oxide layer (15) which has a semiconductor region (5) and a conductor region (7) and in which the semiconductor region overlaps at least partially with a gate electrode (3a) with a first insulating layer (4) interposed between them, a protective layer (8) which covers the channel region of the semiconductor region, and a transparent electrode (9) which is arranged to overlap with at least a portion of the conductor region when viewed along a normal to the substrate (2). An end portion of the oxide layer is at least partially covered with the protective layer.

Abstract: This semiconductor device (100A) includes: an oxide layer (15) which includes a semiconductor region (5) and a conductor region (7) that contacts with the semiconductor region; a source electrode (6s) and a drain electrode (6d) which are electrically connected to the semiconductor region; an insulating layer (11) formed on the source and drain electrodes; a transparent electrode (9) arranged to overlap at least partially with the conductor region with the insulating layer interposed between them; a source line (6a) formed out of the same conductive film as the source electrode; and a gate extended line (3a) formed out of the same conductive film as a gate electrode (3). The source line is electrically connected to the gate extended line via a transparent connecting layer (9a) which is formed out of the same conductive film as the transparent electrode.

Abstract: This semiconductor device (100) includes: a gate electrode (3); a gate insulating layer (4); an oxide layer (50) which is formed on the gate insulating layer (4) and which includes a first conductor region (55) and a first semiconductor region (51) that overlaps at least partially with the gate electrode (3) with the gate insulating layer (4) interposed between them; a source electrode (6s) formed to contact with the upper surface of the first semiconductor region (51) of the oxide layer (50); a drain electrode (6d) which is formed to contact with the upper surface of the first semiconductor region (51) of the oxide layer (50) and which is electrically connected to the first conductor region (55); and a conductive layer (60) which is formed in contact with the upper surface of the oxide layer (50) and which a plurality of holes (66) or notches.

Abstract: The TFT substrate (10) of this liquid crystal display device (100) includes: a TFT (11) which is provided for each pixel; an upper electrode (12) which is electrically connected to the TFT's drain electrode (11d); a lower electrode (13) which is arranged under the upper electrode; and a dielectric layer (14) which is arranged between the upper and lower electrodes. Its counter substrate (20) includes a counter electrode (21) which faces the upper electrode. The upper electrode has first and second regions (R1, R2) which have mutually different electrode structures, and a third region (R3) which electrically connects the first and second regions to the drain electrode. The third region of the upper electrode includes a symmetrical connecting portion (12c) that is a conductive film pattern, of which the shape is substantially symmetrical with respect to a virtual line (L1) that splits each pixel into two adjacent regions in a row direction.

Abstract: This semiconductor device (100A) includes: a substrate (1); a gate electrode (3) and a first transparent electrode (2) which are formed on the substrate (1); a first insulating layer (4) formed over the gate electrode (3) and the first transparent electrode (2); an oxide semiconductor layer (5) formed on the first insulating layer (4); source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5); and a second transparent electrode (7) electrically connected to the drain electrode (6d). At least a portion of the first transparent electrode (2) overlaps with the second transparent electrode (7) with the first insulating layer (4) interposed between them, and the oxide semiconductor layer (5) and the second transparent electrode (7) are formed out of the same oxide film.