Patents by Inventor Yasuyuki Ohnishi

Yasuyuki Ohnishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9684207
    Abstract: Provided are: a polymer for alignment films, which enables the production of a liquid crystal display device that is suppressed in image burn-in even if the light irradiation time is reduced; and a liquid crystal display device which is suppressed in image burn-in even if the light irradiation time is reduced. A polymer for alignment films, which has a main chain and a side chain that contains a structure represented by chemical formula —O—C(C6H5)(CO—C6H5)—O—; and a liquid crystal display device which comprises a pair of substrates and a liquid crystal layer that is held between the pair of substrates, and wherein at least one of the substrates has an alignment film, on which a polymer layer for controlling the alignment of liquid crystal molecules is formed, and the alignment film is formed using a polymer for alignment films, which has a main chain and a side chain that contains a structure represented by chemical formula —O—C(C6H5)(CO—C6H5)—O—.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: June 20, 2017
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yasuyuki Ohnishi, Masanobu Mizusaki
  • Patent number: 9291857
    Abstract: Provided is a liquid crystal display device reducing display unevenness and image sticking even though employing a PSA polymerization step in which monomers are added to a liquid crystal layer. The liquid crystal display device includes a pair of substrates, at least one of the substrates including an alignment film and a structure consisting of an organic insulating material; a polymer layer that is formed on the alignment film to control the alignment of liquid crystal molecules; and a liquid crystal layer containing a liquid crystal material, the layer being placed between the pair of substrates, wherein the polymer layer is formed by polymerization of one or more kinds of radical polymerizable monomers contained in the liquid crystal layer, and at least one kind of the radical polymerizable monomers includes a structure which generates radicals through self-cleavage reaction by light irradiation and two or more radical polymerizable groups.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: March 22, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yasuyuki Ohnishi, Masanobu Mizusaki
  • Publication number: 20150234236
    Abstract: Provided are: a polymer for alignment films, which enables the production of a liquid crystal display device that is suppressed in image burn-in even if the light irradiation time is reduced; and a liquid crystal display device which is suppressed in image burn-in even if the light irradiation time is reduced. A polymer for alignment films, which has a main chain and a side chain that contains a structure represented by chemical formula —O—C(C6H5)(CO—C6H5)—O—; and a liquid crystal display device which comprises a pair of substrates and a liquid crystal layer that is held between the pair of substrates, and wherein at least one of the substrates has an alignment film, on which a polymer layer for controlling the alignment of liquid crystal molecules is formed, and the alignment film is formed using a polymer for alignment films, which has a main chain and a side chain that contains a structure represented by chemical formula —O—C(C6H5)(CO—C6H5)—O—.
    Type: Application
    Filed: August 27, 2013
    Publication date: August 20, 2015
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yasuyuki Ohnishi, Masanobu Mizusaki
  • Publication number: 20140139794
    Abstract: Provided is a liquid crystal display device reducing display unevenness and image sticking even though employing a PSA polymerization step in which monomers are added to a liquid crystal layer. The liquid crystal display device includes a pair of substrates, at least one of the substrates including an alignment film and a structure consisting of an organic insulating material; a polymer layer that is formed on the alignment film to control the alignment of liquid crystal molecules; and a liquid crystal layer containing a liquid crystal material, the layer being placed between the pair of substrates, wherein the polymer layer is formed by polymerization of one or more kinds of radical polymerizable monomers contained in the liquid crystal layer, and at least one kind of the radical polymerizable monomers includes a structure which generates radicals through self-cleavage reaction by light irradiation and two or more radical polymerizable groups.
    Type: Application
    Filed: July 27, 2012
    Publication date: May 22, 2014
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yasuyuki Ohnishi, Masanobu Mizusaki
  • Publication number: 20110248252
    Abstract: An organic EL display element (1) includes: an insulating substrate (3); a first electrode (6) formed on the substrate (3); an organic layer (7) having an emitting layer, formed on the first electrode (6); and a second electrode (8) formed on the organic layer (7). A conductive member (2) made of a material higher in thermal conductivity and higher in electrical conductivity than the substrate (3) is formed on a surface (3a) of the substrate (3) opposite to the surface on which the first electrode (6) is formed.
    Type: Application
    Filed: August 17, 2009
    Publication date: October 13, 2011
    Inventors: Yasuyuki Ohnishi, Yoshimasa Fujita, Hideki Uchida
  • Patent number: 7259290
    Abstract: Production and utilization of model mouse, in which human hematopoietic tumor cells can be grown, expressing symptom of human hematopoietic tumor, and can be used in the screening of anticancer drugs for human hematopoietic tumor. The invention provides a new method to produce model mouse for human hematopoietic tumor, including engraftment of human hematopoietic tumor cells into NOG (NOD/Shi-scid, IL-2R? KO) mice.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: August 21, 2007
    Assignee: Central Institute for Experimental Animals
    Inventors: Yoshitaka Miyakawa, Masahiro Kizaki, Yasuo Ikeda, Masato Nakamura, Yasuyuki Ohnishi
  • Publication number: 20070122964
    Abstract: A semiconductor device is equipped with a step-up circuit having a series of multiple charge pump units. Each of the units has a well separation type MOS transistor. The separation well of the transistor is coupled to a high potential so as to form double reverse biases between the N-type well and a P-type substrate and between the N-type well and a P-type well. This permits the threshold Vth of the MOS transistor to be held at low level. The units are provided with a clock whose current supply capability is limited until a predetermined condition (that a predetermined period of time has elapsed after the onset of the step-up circuit by a startup signal or that the output voltage has reached a predetermined level). This limitation of the clock facilitates suppression of power consumption by the step-up circuit during a startup, thereby reducing changes in amplitude of a supply voltage.
    Type: Application
    Filed: January 30, 2007
    Publication date: May 31, 2007
    Applicant: ROHM CO., LTD.
    Inventors: Michio NAKAGAWA, Kazuo SATO, Hiromi UENOYAMA, Yasuyuki OHNISHI, Kazunori TORII
  • Publication number: 20070092881
    Abstract: The invention concerns the study of tumor metastasis in a NOD/SCID/?cnull transgenic mouse model and the identification of tumor markers, including markers of tumors with high metastatic potential, using information obtained in this mouse model.
    Type: Application
    Filed: September 29, 2004
    Publication date: April 26, 2007
    Applicants: CENTRAL INSTITUTE FOR EXPERIMENTAL ANIMALS, CHUGAI PHARMACEUTICAL, INC., CENTER FOR THE ADVANCEMENT OF HEALTH AND BIOSCIENCE, USA
    Inventors: Yasuyuki Ohnishi, Masato Nakamura, Hiroshi Suemizu, Makoto Monnai
  • Patent number: 7190211
    Abstract: A semiconductor device is equipped with a step-up circuit having a series of multiple charge pump units. Each of the units has a well separation type MOS transistor. The separation well of the transistor is coupled to a high potential so as to form double reverse biases between the N-type well and a P-type substrate and between the N-type well and a P-type well. This permits the threshold Vth of the MOS transistor to be held at low level. The units are provided with a clock whose current supply capability is limited until a predetermined condition (that a predetermined period of time has elapsed after the onset of the step-up circuit by a startup signal or that the output voltage has reached a predetermined level). This limitation of the clock facilitates suppression of power consumption by the step-up circuit during a startup, thereby reducing changes in amplitude of a supply voltage.
    Type: Grant
    Filed: February 15, 2005
    Date of Patent: March 13, 2007
    Assignee: Rohm Co., Ltd.
    Inventors: Michio Nakagawa, Kazuo Sato, Hiromi Uenoyama, Yasuyuki Ohnishi, Kazunori Torii
  • Publication number: 20050249666
    Abstract: The invention provides a new reproducible transgenic mouse model for the study of tumor metastasis. In particular, the invention concerns the study of tumor metastasis in a NOD/SCID/?cnull transgenic mouse model.
    Type: Application
    Filed: September 29, 2004
    Publication date: November 10, 2005
    Applicants: CENTRAL INSTITUTE FOR EXPERIMENTAL ANIMALS, CENTER FOR THE ADVANCEMENT OF HEALTH AND BIOSCIENCE, USA
    Inventors: Masato Nakamura, Yasuyuki Ohnishi, Hiroshi Suemizu, Makoto Monnai
  • Publication number: 20050134362
    Abstract: A semiconductor device is equipped with a step-up circuit having a series of multiple charge pump units. Each of the units has a well separation type MOS transistor. The separation well of the transistor is coupled to a high potential so as to form double reverse biases between the N-type well and a P-type substrate and between the N-type well and a P-type well. This permits the threshold Vth of the MOS transistor to be held at low level. The units are provided with a clock whose current supply capability is limited until a predetermined condition (that a predetermined period of time has elapsed after the onset of the step-up circuit by a startup signal or that the output voltage has reached a predetermined level). This limitation of the clock facilitates suppression of power consumption by the step-up circuit during a startup, thereby reducing changes in amplitude of a supply voltage.
    Type: Application
    Filed: February 15, 2005
    Publication date: June 23, 2005
    Inventors: Michio Nakagawa, Kazuo Sato, Hiromi Uenoyama, Yasuyuki Ohnishi, Kazunori Torii
  • Publication number: 20050132427
    Abstract: The invention provides a new reproducible transgenic mouse model for the study of tumor metastasis. In particular, the invention concerns the study of tumor metastasis in a NOD/SCID/?cnull transgenic mouse model.
    Type: Application
    Filed: June 18, 2004
    Publication date: June 16, 2005
    Inventors: Masato Nakamura, Yasuyuki Ohnishi
  • Patent number: 6888399
    Abstract: A semiconductor device is equipped with a step-up circuit having a series of multiple charge pump units. Each of the units has a well separation type MOS transistor. The separation well of the transistor is coupled to a high potential so as to form double reverse biases between the N-type well and a P-type substrate and between the N-type well and a P-type well. This permits the threshold Vth of the MOS transistor to be held at low level. The units are provided with a clock whose current supply capability is limited until a predetermined condition (that a predetermined period of time has elapsed after the onset of the step-up circuit by a startup signal or that the output voltage has reached a predetermined level). This limitation of the clock facilitates suppression of power consumption by the step-up circuit during a startup, thereby reducing changes in amplitude of a supply voltage.
    Type: Grant
    Filed: February 4, 2003
    Date of Patent: May 3, 2005
    Assignee: Rohm Co., Ltd.
    Inventors: Michio Nakagawa, Kazuo Sato, Hiromi Uenoyama, Yasuyuki Ohnishi, Kazunori Torii
  • Publication number: 20030165954
    Abstract: The present invention relates to genetic profiles and markers of cancers and provides systems and methods for screening drugs that are effective for specific patients and types of cancers. In particular, the present invention provides personalized treatment customized to an individual's cancer.
    Type: Application
    Filed: January 9, 2003
    Publication date: September 4, 2003
    Applicant: Third Wave Technologies, Inc.
    Inventors: Toyomasa Katagiri, Yasuyuki Ohnishi, Yusuke Nakamura
  • Publication number: 20030151449
    Abstract: A semiconductor device is equipped with a step-up circuit having a series of multiple charge pump units. Each of the units has a well separation type MOS transistor. The separation well of the transistor is coupled to a high potential so as to form double reverse biases between the N-type well and a P-type substrate and between the N-type well and a P-type well. This permits the threshold Vth of the MOS transistor to be held at low level. The units are provided with a clock whose current supply capability is limited until a predetermined condition (that a predetermined period of time has elapsed after the onset of the step-up circuit by a startup signal or that the output voltage has reached a predetermined level). This limitation of the clock facilitates suppression of power consumption by the step-up circuit during a startup, thereby reducing changes in amplitude of a supply voltage.
    Type: Application
    Filed: February 4, 2003
    Publication date: August 14, 2003
    Applicant: ROHM CO., LTD.
    Inventors: Michio Nakagawa, Kazuo Sato, Hiromi Uenoyama, Yasuyuki Ohnishi, Kazunori Torii
  • Patent number: 5973873
    Abstract: In a motor control circuit for a VCR, a microcomputer calculates a center frequency to be targeted by a drum motor based on frequency pulses from the capstan motor, and generates a speed control signal for the drum motor based on a frequency deviation of the drum motor from the center frequency. Thus, in the motor control circuit, color misplacement occurring during a tape speed change is eliminated easily and surely.
    Type: Grant
    Filed: October 4, 1996
    Date of Patent: October 26, 1999
    Assignee: Rohm Co., Ltd.
    Inventor: Yasuyuki Ohnishi
  • Patent number: 5726822
    Abstract: A motor control circuit generates a signal representing a rotation frequency of a motor. It produces a motor speed error signal based on the rotation frequency. The error signal is changed by a speed gain circuit and supplied to the motor driving circuit through a filter. The filter is for preventing an oscillation in a servo loop. When the motor speed is out of a predetermined range, a gain of the speed error signal is reduced and the filter is disabled.
    Type: Grant
    Filed: April 25, 1996
    Date of Patent: March 10, 1998
    Assignee: Rohm Co., Ltd.
    Inventors: Yo Sawamura, Yasuyuki Ohnishi
  • Patent number: 5689163
    Abstract: A motor controller of the present invention has a frequency generator which outputs, in accordance with a rotation of the motor, a predetermined number of rotational signals every time the motor makes one rotation. A period signal representative of the period of the rotational signals is calculated, and the period signal and a predetermined value are subtracted to obtain a speed error signal. The error signal is stored at a predetermined address of a memory. A filter which performs filtering by use of a plurality of error signals in the memory and a subtracter which subtracts the error signals and the contents of the memory are provided. A selecting circuit outputs the error signal when the error signal is outside a predetermined range and outputs an output of the filter when the error signal is within the predetermined range. Thereafter, the selecting circuit outputs an output signal of the subtracter. A control signal is produced from an output of the selecting circuit.
    Type: Grant
    Filed: October 24, 1995
    Date of Patent: November 18, 1997
    Assignee: Rohm Co. Ltd.
    Inventor: Yasuyuki Ohnishi