Patents by Inventor Yasuyuki Okada

Yasuyuki Okada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050139987
    Abstract: A semiconductor integrated circuit device comprises: a semiconductor integrated circuit chip mounted on a semiconductor base, the semiconductor integrated circuit chip having a plurality of circuit systems mounted being separated and driven by different electric power source systems and also having at least one electrostatic protection circuit; and an outer connecting terminal 5 connected to the circuit systems of the semiconductor integrated circuit chip via a wiring member 4 having at least one wiring layer, wherein electric power source lines and ground lines of the plurality of circuit systems of the semiconductor integrated circuit chip 1 are respectively commonly connected on a conductive plane 43, which is provided in the wiring member, via an electrostatic protection circuit 2.
    Type: Application
    Filed: November 12, 2004
    Publication date: June 30, 2005
    Inventors: Yasuyuki Okada, Hiroyuki Miyazaki, Masumi Nobata
  • Publication number: 20050066098
    Abstract: In a priority circuit, priority processing is rapidly performed without lowering the voltage level of a signal propagated through serially connected transistors. When the priority circuit is placed in a non-operational state by turning off an NMOS transistor in accordance with a precharge enable signal, potentials on propagating signal nodes and a HIT output terminal are precharged to H potential by PMOS transistors used for precharging. Therefore, when the NMOS transistor is turned on and the priority circuit enters an operational state, if input signals include a H-level signal, the lowering of the voltage level of a propagated signal is suppressed in increasing the potentials on the propagating signal nodes and the HIT output terminal to the H potential by PMOS transistors used for detecting a HIT signal. Thus, malfunction derived from noise can be prevented.
    Type: Application
    Filed: September 9, 2004
    Publication date: March 24, 2005
    Inventors: Yorimasa Funahashi, Yasuyuki Okada
  • Publication number: 20050007698
    Abstract: A thin film magnetic head and a method of manufacture thereof, wherein the head includes a lower magnetic pole, an upper magnetic pole provided so as to face the lower magnetic pole, and a magnetic gap layer provided between the lower magnetic pole and the upper magnetic pole. The upper magnetic pole is formed by a sputtered first magnetic layer which is an underlayer and a plated second magnetic layer provided on the sputtered first magnetic layer.
    Type: Application
    Filed: August 10, 2004
    Publication date: January 13, 2005
    Inventors: Kazue Kudo, Yasuyuki Okada, Moriaki Fuyama, Yohji Maruyama, Gen Oikawa
  • Publication number: 20040245656
    Abstract: To provide a semiconductor device which can be down-sized and integrated to a high degree.
    Type: Application
    Filed: March 26, 2004
    Publication date: December 9, 2004
    Inventors: Akinori Haza, Yasuyuki Okada, Masumi Nobata
  • Publication number: 20040240488
    Abstract: An optical fiber laser includes a resonator comprising an erbium-doped glass fiber serving as a gain medium and a pumping light source that launches pumping light into the erbium-doped glass fiber. The pumping light source emits pumping light of a wavelength of 980 nm or longer, and the optical fiber laser emits laser light in a wavelength band of 2.8 &mgr;m (2.7 &mgr;m to 3.0 &mgr;m).
    Type: Application
    Filed: June 1, 2004
    Publication date: December 2, 2004
    Applicant: FUJIKURA LTD.
    Inventors: Yasuyuki Okada, Takeshi Segi, Tetsuya Sakai
  • Patent number: 6801062
    Abstract: In a first and second logic circuit controlling a driver circuit of CMOS configuration having a plurality of output transistors connected in parallel, a delay fluctuation clock signal and a delay fluctuation data signal are generated by generating multi-phase data signals from multi-phase clock signals that each have a different phase difference with respect to a reference clock signal, and using a delay circuit having a variable delay time reflecting the change of the current driving capability of the output transistors in the driver circuit. Then, changes in the current driving capability of the output transistors are detected from a phase relation between the multi-phase data signals and the delay fluctuation data signal, and if it is detected that the current driving capability has decreased, then the number of output transistors that become conducting is increased, whereas if it is detected that the current driving capability has increased, then their number is decreased.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: October 5, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Yasuyuki Okada
  • Patent number: 6795272
    Abstract: A thin film magnetic head includes a lower magnetic pole, an upper magnetic pole provided so as to face the lower magnetic pole, and a magnetic gap layer provided between the lower magnetic pole and the upper magnetic pole. The upper magnetic pole constitutes a first magnetic layer formed on a side facing the magnetic gap layer by means of sputtering and a second magnetic layer formed on the first magnetic layer by means of plating, in which the saturation magnetic flux density of the first magnetic layer is set higher than that of the second magnetic layer. The thin film magnetic head composed as above is capable of generating a stronger magnetic field owing to its stably-formed magnetic core, thereby recording on a high-coercivity medium and high-density recording are made possible.
    Type: Grant
    Filed: August 14, 2002
    Date of Patent: September 21, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Kazue Kudo, Yasuyuki Okada, Moriaki Fuyama, Yohji Maruyama, Gen Oikawa
  • Patent number: 6794063
    Abstract: The present invention provides a thin film magnetic head having sufficient recording performance on a recording medium imparted with a large coercive force. According to the present invention, a plated magnetic thin film can be obtained in which a crystal grain size is modulated in a film thickness direction and a coercive force is reduced. Further, according to the present invention, even for a composition area indicating a high saturation magnetic flux density in which, conventionally, soft magnetic properties could not be obtained, magnetic film having an excellent soft magnetic property can be manufactured.
    Type: Grant
    Filed: May 24, 2002
    Date of Patent: September 21, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yasuyuki Okada, Kazue Kudo, Hiroyuki Hoshiya
  • Publication number: 20040169959
    Abstract: A material for magnetic pole for attaining a writing head generating an intense recording magnetic field, and a structure and a manufacturing method therefor. The thin film magnetic head includes a magnetic pole layer having a plated magnetic layer containing Co, Ni and Fe formed on a plated underlayer of a sputtered magnetic layer containing Co, Ni and Fe. The CoNiFe magnetic layer having a composition: 40 wt %≦Co≦70 wt %, 10 wt %≦Ni≦25 wt % and 10 wt %≦Fe≦30 wt % and a peak intensity ratio in the X-ray diffraction of I(200)/I(111)≧0.5 and I(110)/I(111)≧1 (defining peak intensities for the face-centered cubic fcc (111) face, fcc (200) face and the body-centered cubic bcc (119) face as: I(111), I(200), I(110)).
    Type: Application
    Filed: March 9, 2004
    Publication date: September 2, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Kazue Kudo, Yasuyuki Okada, Nobuo Yoshida, Moriaki Fuyama, Noriyuki Saiki, Gen Oikawa, Takashi Kawabe, Makoto Morijiri
  • Publication number: 20040150912
    Abstract: Thin film perpendicular magnetic head with a narrow main pole capable of a high recording density in excess of 100 gigabits per square inch and generating a high magnetic recording field exceeding 10 kOe (oersted), while also modified to suppress remanent magnetic fields occurring immediately after writing operation. In a perpendicular magnetic head comprising a main pole, a return path for supplying a magnetic flux to that main pole, and an conductive coil for excitation of the main pole and return path, the main pole has a pole width of 200 nanometers or less, and a magnetic multilayer made up of a high saturation flux density layer and low saturation flux density layer, the low saturation flux density layer has a thickness within 0.5 to 5 nanometers, the high saturation flux density layer has a thickness from 10 to 50 nanometers for suppressing remanent magnetization and preventing erasing after writing by utilizing a closed magnetic domain structure in the pole.
    Type: Application
    Filed: August 20, 2003
    Publication date: August 5, 2004
    Inventors: Yoshiaki Kawato, Kazuhiro Nakamoto, Hiroyuki Hoshiya, Yasuyuki Okada, Masafumi Mochizuki
  • Publication number: 20040150007
    Abstract: A different electric power supply electric power source cell is proposed which includes paths by which electric power source voltages, the electric potentials of which are different from each other, are respectively taken in from the area pad and the probing pad and by which the voltages are supplied to the blocks requiring these electric power source voltages.
    Type: Application
    Filed: December 22, 2003
    Publication date: August 5, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Takaaki Kumagae, Yasuyuki Okada, Masumi Nobata
  • Publication number: 20040120074
    Abstract: The disclosed invention provides a magnetic head of high stability in which “erase after write” is prevented. Here is provided a magnetic head comprising a thin-film magnetic head for perpendicular magnetic recording, the thin-film magnetic head including a main pole with its tip facing a magnetic recording medium and coils for exciting the main pole, wherein the tip of or at least a part of the main pole consists of a soft magnetic multilayer containing laminations, each of which comprises a first ferromagnetic film, a second ferromagnetic film, and an antiparallel coupling layer formed between the first ferromagnetic film and the second ferromagnetic film, wherein the antiparallel coupling layer causes antiferromagnetic interlayer coupling of the first ferromagnetic film and the second ferromagnetic film.
    Type: Application
    Filed: July 2, 2003
    Publication date: June 24, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Yasuyuki Okada, Hiroyuki Hoshiya, Yoshiaki Kawato
  • Patent number: 6723449
    Abstract: A material for magnetic pole for attaining a writing head generating an intense recording magnetic field, and a structure and a manufacturing method therefor. The thin film magnetic head includes a magnetic pole layer having a plated magnetic layer containing Co, Ni and Fe formed on a plated underlayer of a sputtered magnetic layer containing Co, Ni and Fe. The CoNiFe magnetic layer having a composition: 40 wt %≦Co≦70 wt %, 10 wt %≦Ni≦25 wt % and 10 wt %≦Fe≦30 wt % and a peak intensity ratio in the X-ray diffraction of I(200)/I(111)≧0.5 and I(110)/I(111)≧1 (defining peak intensities for the face-centered cubic fcc (111) face, fcc (200) face and the body-centered cubic bcc (119) face as: I(111), I(200), I(110)).
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: April 20, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Kazue Kudo, Yasuyuki Okada, Nobuo Yoshida, Moriaki Fuyama, Noriyuki Saiki, Gen Oikawa, Takashi Kawabe, Makoto Morijiri
  • Publication number: 20030137326
    Abstract: In a first and second logic circuit controlling a driver circuit of CMOS configuration having a plurality of output transistors connected in parallel, a delay fluctuation clock signal and a delay fluctuation data signal are generated by generating multi-phase data signals from multi-phase clock signals that each have a different phase difference with respect to a reference clock signal, and using a delay circuit having a variable delay time reflecting the change of the current driving capability of the output transistors in the driver circuit. Then, changes in the current driving capability of the output transistors are detected from a phase relation between the multi-phase data signals and the delay fluctuation data signal, and if it is detected that the current driving capability has decreased, then the number of output transistors that become conducting is increased, whereas if it is detected that the current driving capability has increased, then their number is decreased.
    Type: Application
    Filed: January 17, 2003
    Publication date: July 24, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventor: Yasuyuki Okada
  • Publication number: 20030095357
    Abstract: A thin film magnetic head includes a lower magnetic pole, an upper magnetic pole provided so as to face the lower magnetic pole, and a magnetic gap layer provided between the lower magnetic pole and the upper magnetic pole. The upper magnetic pole constitutes a first magnetic layer formed on a side facing the magnetic gap layer by means of sputtering and a second magnetic layer formed on the first magnetic layer by means of plating, in which the saturation magnetic flux density of the first magnetic layer is set higher than that of the second magnetic layer. The thin film magnetic head composed as above is capable of generating a stronger magnetic field owing to its stably-formed magnetic core, thereby recording on a high-coercivity medium and high-density recording are made possible.
    Type: Application
    Filed: August 14, 2002
    Publication date: May 22, 2003
    Inventors: Kazue Kudo, Yasuyuki Okada, Moriaki Fuyama, Yohji Maruyama, Gen Oikawa
  • Patent number: 6546471
    Abstract: A shared memory multiprocessor (SMP) has efficient access to a main memory included in a particular node and a management of partitions that include the nodes. In correspondence with each page of main memory included in a node, a bit stored in a register indicates if the page has been accessed from any other node. In a case where the bit is “0”, a cache coherent command to be sent to the other nodes is not transmitted. The bit is reset by software at the time of initialization and memory allocation, and it is set by hardware when the page of the main memory is accessed from any other node. In a case where the interior of an SMP is divided into partitions, the main memory of each node is divided into local and shared areas, for which respectively separate addresses can be designated. In each node, the configuration information items of the shared area and the local area are stored in registers.
    Type: Grant
    Filed: February 18, 2000
    Date of Patent: April 8, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Toshiaki Tarui, Koichi Okazawa, Yasuyuki Okada, Toru Shonai, Toshio Okochi, Hideya Akashi
  • Publication number: 20020192503
    Abstract: The present invention provides a thin film magnetic head having sufficient recording performance on a recording medium imparted with a large coercive force. According to the present invention, a plated magnetic thin film can be obtained in which a crystal grain size is modulated in a film thickness direction and a coercive force is reduced. Further, according to the present invention, even for a composition area indicating a high saturation magnetic flux density in which, conventionally, soft magnetic properties could not be obtained, magnetic film having an excellent soft magnetic property can be manufactured.
    Type: Application
    Filed: May 24, 2002
    Publication date: December 19, 2002
    Inventors: Yasuyuki Okada, Kazue Kudo, Hiroyuki Hoshiya
  • Publication number: 20020106533
    Abstract: A material for magnetic pole for attaining a writing head generating an intense recording magnetic field, and a structure and a manufacturing method therefor. The thin film magnetic head includes a magnetic pole layer having a plated magnetic layer containing Co, Ni and Fe formed on a plated underlayer of a sputtered magnetic layer containing Co, Ni and Fe. The CoNiFe magnetic layer having a composition: 40 wt %≦Co≦70 wt %, 10 wt %≦Ni≦25 wt % and 10 wt %≦Fe≦30 wt % and a peak intensity ratio in the X-ray diffraction of I(200)/I(111)≧0.5 and I(110)/I(111)≧1 (defining peak intensities for the face-centered cubic fcc (111) face, fcc (200) face and the body-centered cubic bcc (119) face as: I(111), I(200), I(110)).
    Type: Application
    Filed: July 31, 2001
    Publication date: August 8, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Kazue Kudo, Yasuyuki Okada, Nobuo Yoshida, Moriaki Fuyama, Noriyuki Saiki, Gen Oikawa, Takashi Kawabe, Makoto Morijiri
  • Patent number: 6378021
    Abstract: In an information processing apparatus having a crossbar switch, registers are provided for logical division of a connection of the crossbar switch into a plurality of groups, in order to allow a system to change the group division configuration while the system is in an ordinary operation. As an application of this, in a hot standby system, when a fault occurs in an active partition and the active partition is replaced by a standby partition, the standby partition is allowed to include system resources used by the active partition such as CPU's and memories.
    Type: Grant
    Filed: February 16, 1999
    Date of Patent: April 23, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Koichi Okazawa, Toshiaki Tarui, Yasuyuki Okada
  • Patent number: 6131169
    Abstract: An information processing apparatus includes a crossbar switch having a plurality of switching circuits for data transfer; connection lines having address data transfer paths of m-bit unit connected to each of the input/output ports of the switching circuits, control signal transfer paths of m-bit unit connected to each of the input/output ports of the control circuits and back-up transfer paths of m-bit unit connected to each of the input/output ports of the back-up circuits; and transfer path processing circuit connected correspondingly to the connection lines constructed by the n-bit provided on each of the processing units, monitored transfer of data and control signal between the processing units through the switching circuit and the control circuit in the crossbar switch, and detected a failure of at least the switching circuit and the control circuit to thereby change the connection of at least one of the failed switching circuit and control circuit to a connection of the back-up circuit.
    Type: Grant
    Filed: December 14, 1999
    Date of Patent: October 10, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Koichi Okazawa, Toshiaki Tarui, Yasuyuki Okada