Patents by Inventor Yau Ning Chin

Yau Ning Chin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180321966
    Abstract: Various aspects are disclosed herein for attenuating spin waiting in a virtual machine environment comprising a plurality of virtual machines and virtual processors. Selected virtual processors can be given time slice extensions in order to prevent such virtual processors from becoming de-scheduled (and hence causing other virtual processors to have to spin wait). Selected virtual processors can also be expressly scheduled so that they can be given higher priority to resources, resulting in reduced spin waits for other virtual processors waiting on such selected virtual processors. Finally, various spin wait detection techniques can be incorporated into the time slice extension and express scheduling mechanisms, in order to identify potential and existing spin waiting scenarios.
    Type: Application
    Filed: July 10, 2018
    Publication date: November 8, 2018
    Inventors: Yau Ning Chin, John Te-Jui Sheu, Arun Kishan, Thomas Fahrig, Rene Antonio Vega
  • Patent number: 10067782
    Abstract: Various aspects are disclosed herein for attenuating spin waiting in a virtual machine environment comprising a plurality of virtual machines and virtual processors. Selected virtual processors can be given time slice extensions in order to prevent such virtual processors from becoming de-scheduled (and hence causing other virtual processors to have to spin wait). Selected virtual processors can also be expressly scheduled so that they can be given higher priority to resources, resulting in reduced spin waits for other virtual processors waiting on such selected virtual processors. Finally, various spin wait detection techniques can be incorporated into the time slice extension and express scheduling mechanisms, in order to identify potential and existing spin waiting scenarios.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: September 4, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Yau Ning Chin, John Te-Jui Sheu, Arun Kishan, Thomas Fahrig, Rene Antonio Vega
  • Publication number: 20160154666
    Abstract: Various aspects are disclosed herein for attenuating spin waiting in a virtual machine environment comprising a plurality of virtual machines and virtual processors. Selected virtual processors can be given time slice extensions in order to prevent such virtual processors from becoming de-scheduled (and hence causing other virtual processors to have to spin wait). Selected virtual processors can also be expressly scheduled so that they can be given higher priority to resources, resulting in reduced spin waits for other virtual processors waiting on such selected virtual processors. Finally, various spin wait detection techniques can be incorporated into the time slice extension and express scheduling mechanisms, in order to identify potential and existing spin waiting scenarios.
    Type: Application
    Filed: November 18, 2015
    Publication date: June 2, 2016
    Inventors: Yau Ning Chin, John Te-Jui Sheu, Arun Kishan, Thomas Fahrig
  • Patent number: 9201673
    Abstract: Various aspects are disclosed herein for attenuating spin waiting in a virtual machine environment comprising a plurality of virtual machines and virtual processors. Selected virtual processors can be given time slice extensions in order to prevent such virtual processors from becoming de-scheduled (and hence causing other virtual processors to have to spin wait). Selected virtual processors can also be expressly scheduled so that they can be given higher priority to resources, resulting in reduced spin waits for other virtual processors waiting on such selected virtual processors. Finally, various spin wait detection techniques can be incorporated into the time slice extension and express scheduling mechanisms, in order to identify potential and existing spin waiting scenarios.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: December 1, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Yau Ning Chin, Rene Antonio Vega, John Te-Jui Sheu, Arun Kishan, Thomas Fahrig
  • Patent number: 8645592
    Abstract: Techniques are disclosed for managing the flow of IO jobs from a client to a hardware device such that resource starvation is reduced without significantly impacting throughput. Each flow can be assigned an amount of time that a hardware device can deplete completing IO jobs from the client. When the allocated amount of time is used IO jobs associated with the client can be stored in a queue until the client obtains more time.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: February 4, 2014
    Assignee: Microsoft Corporation
    Inventors: Dustin L. Green, Yau Ning Chin, Bruce L. Worthington
  • Patent number: 8479214
    Abstract: Improved hardware throughput can be achieved when a hardware device is saturated with IO jobs. Throughput can be estimated based on the quantifiable characteristics of incoming IO jobs. When IO jobs are received a time cost for each job can be estimated and stored in memory. The estimates can be used to calculate the total time cost of in-flight IO jobs and a determination can be made as to whether the hardware device is saturated based on completion times for IO jobs. Over time the time cost estimates for IO jobs can be revised based on a comparison between the estimated time cost for an IO job and the actual time cost for the IO job using aggregate IO job completion sequences.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: July 2, 2013
    Assignee: Microsoft Corporation
    Inventors: Dustin L. Green, Yau Ning Chin, Bruce L. Worthington
  • Patent number: 8346995
    Abstract: Techniques are disclosed for managing the flow of IO jobs from a client to a hardware device such that resource starvation is reduced without significantly impacting throughput. Each flow can be assigned an amount of time that a hardware device can deplete completing IO jobs from the client. When the allocated amount of time is used IO jobs associated with the client can be stored in a queue until the client obtains more time.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: January 1, 2013
    Assignee: Microsoft Corporation
    Inventors: Dustin L. Green, Yau Ning Chin, Bruce L. Worthington
  • Patent number: 8245229
    Abstract: Batching techniques are provided to maximize the throughput of a hardware device based on the saturation point of the hardware device. A balancer can determine the saturation point of the hardware device and determine the estimated time cost for IO jobs pending in the hardware device. A comparison can be made and if the estimated time cost total is lower than the saturation point one or more IO jobs can be sent to the hardware device.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: August 14, 2012
    Assignee: Microsoft Corporation
    Inventors: Dustin L. Green, Yau Ning Chin, Bruce L. Worthington, Shuvabrata Ganguly, Pankaj Garg
  • Patent number: 7913009
    Abstract: Example operations related to deferring interrupts are herein disclosed. In one example embodiment, a method includes, but is not limited to, writing a message to a memory location shared between a sender and a receiver; and requesting that an interrupt be transmitted to the receiver after a specified latency has elapsed, wherein an interrupt that is pending is stored in a trigger memory. It can be appreciated by one of skill in the art that one or more various aspects of the disclosure may include but are not limited to circuitry and/or programming for effecting the herein-referenced aspects; the circuitry and/or programming can be virtually any combination of hardware, software, and/or firmware configured to effect the herein-referenced aspects depending upon the design choices of the system designer. In addition to the foregoing, other aspects are described in the claims, drawings, and text forming a part of the present application.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: March 22, 2011
    Assignee: Microsoft Corporation
    Inventors: René Vega, John Te-Jui Sheu, Yau Ning Chin
  • Publication number: 20100083256
    Abstract: Batching techniques are provided to maximize the throughput of a hardware device based on the saturation point of the hardware device. A balancer can determine the saturation point of the hardware device and determine the estimated time cost for IO jobs pending in the hardware device. A comparison can be made and if the estimated time cost total is lower than the saturation point one or more IO jobs can be sent to the hardware device.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 1, 2010
    Applicant: Microsoft Corporation
    Inventors: Dustin L. Green, Yau Ning Chin, Bruce L. Worthington, Shuvabrata Ganguly, Pankaj Garg
  • Publication number: 20100083274
    Abstract: Improved hardware throughput can be achieved when a hardware device is saturated with IO jobs. Throughput can be estimated based on the quantifiable characteristics of incoming IO jobs. When IO jobs are received a time cost for each job can be estimated and stored in memory. The estimates can be used to calculate the total time cost of in-flight IO jobs and a determination can be made as to whether the hardware device is saturated based on completion times for IO jobs. Over time the time cost estimates for IO jobs can be revised based on a comparison between the estimated time cost for an IO job and the actual time cost for the IO job using aggregate IO job completion sequences.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 1, 2010
    Applicant: Microsoft Corporation
    Inventors: Dustin L. Green, Yau Ning Chin, Bruce L. Worthington
  • Publication number: 20100082851
    Abstract: Techniques are disclosed for managing the flow of IO jobs from a client to a hardware device such that resource starvation is reduced without significantly impacting throughput. Each flow can be assigned an amount of time that a hardware device can deplete completing IO jobs from the client. When the allocated amount of time is used IO jobs associated with the client can be stored in a queue until the client obtains more time.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 1, 2010
    Applicant: Microsoft Corporation
    Inventors: Dustin L. Green, Yau Ning Chin, Bruce L. Worthington
  • Publication number: 20100031254
    Abstract: Various aspects are disclosed herein for attenuating spin waiting in a virtual machine environment comprising a plurality of virtual machines and virtual processors. Selected virtual processors can be given time slice extensions in order to prevent such virtual processors from becoming de-scheduled (and hence causing other virtual processors to have to spin wait). Selected virtual processors can also be expressly scheduled so that they can be given higher priority to resources, resulting in reduced spin waits for other virtual processors waiting on such selected virtual processors. Finally, various spin wait detection techniques can be incorporated into the time slice extension and express scheduling mechanisms, in order to identify potential and existing spin waiting scenarios.
    Type: Application
    Filed: July 30, 2008
    Publication date: February 4, 2010
    Applicant: Microsoft Corporation
    Inventors: Yau Ning Chin, Rene Antonio Vega, John Te-Jui Sheu, Arun Kishan, Thomas Fahrig
  • Publication number: 20080320194
    Abstract: Example operations related to deferring interrupts are herein disclosed. In one example embodiment, a method includes, but is not limited to, writing a message to a memory location shared between a sender and a receiver; and requesting that an interrupt be transmitted to the receiver after a specified latency has elapsed, wherein an interrupt that is pending is stored in a trigger memory. It can be appreciated by one of skill in the art that one or more various aspects of the disclosure may include but are not limited to circuitry and/or programming for effecting the herein-referenced aspects; the circuitry and/or programming can be virtually any combination of hardware, software, and/or firmware configured to effect the herein-referenced aspects depending upon the design choices of the system designer. In addition to the foregoing, other aspects are described in the claims, drawings, and text forming a part of the present application.
    Type: Application
    Filed: June 20, 2007
    Publication date: December 25, 2008
    Applicant: Microsoft Corporation
    Inventors: Rene Vega, John Te-Jui Sheu, Yau Ning Chin