Patents by Inventor Yen-An CHEN

Yen-An CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942519
    Abstract: A semiconductor structure includes a superlattice structure, an electrical isolation layer, a channel layer, and a composition gradient layer. The superlattice structure is disposed on a substrate, the electrical isolation layer is disposed on the superlattice structure, the channel layer is disposed on the electrical isolation layer, and the composition gradient layer is disposed between the electrical isolation layer and the superlattice structure. The composition gradient layer and the superlattice structure include a same group III element, and the atomic percentage of the same group III element in the composition gradient layer is gradually decreased in the direction from the superlattice structure to the electrical isolation layer. In addition, a high electron mobility transistor including the semiconductor structure is also provided.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: March 26, 2024
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chih-Yen Chen, Franky Juanda Lumbantoruan
  • Patent number: 11937574
    Abstract: An interactive device for animals is provided that includes a main body, a driving module and a first rotating member. The main body includes an accommodating groove, an opening, and a communicating channel. The driving module is disposed on the main body. The first rotating member is rotatably disposed in the main body and separates the communicating channel and the accommodating groove. When the driving module drives the first rotating member to rotate in a first rotating direction, the first rotating member drives at least one object disposed in the accommodating groove to enter the communicating channel and leave the main body through the opening.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: March 26, 2024
    Assignee: TOMOFUN CO., LTD.
    Inventors: Chia-Yen Chang, Min-Wei Chen, Yo-Chen Victor Chang
  • Publication number: 20240098909
    Abstract: An electronic device includes a first component and a second component. The first component includes a first housing and a protrusion element. The first housing has a first cover plate, and the protrusion element is disposed on the first cover plate. The second component is rotationally assembled with the first component along a first direction. The second component includes a second housing, an elastic structure, and a switching element. The elastic structure has an elastic post. The second housing has a second cover plate having a through hole. One part of the elastic post passes through the through hole and is exposed on the second cover plate. The protrusion element moves along a first direction relative to the elastic structure, such that the elastic post is squeezed by the protrusion element to move along a second direction and presses the switching element.
    Type: Application
    Filed: June 16, 2023
    Publication date: March 21, 2024
    Inventors: HSIN-CHANG LIN, BO-YEN CHEN
  • Publication number: 20240097010
    Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Inventors: Sai-Hooi Yeong, Sheng-Chen Wang, Bo-Yu Lai, Ziwei Fang, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20240096757
    Abstract: An integrated circuit (IC) die includes first through third adjacent rows of through-silicon vias (TSVs), and first and second adjacent rows of memory macros. TSVs of the first row of TSVs extend through and are electrically isolated from memory macros of the first row of memory macros. TSVs of the third row of TSVs extend through and are electrically isolated from memory macros of the second row of memory macros.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Inventors: Hidehiro FUJIWARA, Tze-Chiang HUANG, Hong-Chen CHENG, Yen-Huei CHEN, Hung-Jen LIAO, Jonathan Tsung-Yung CHANG, Yun-Han LEE, Lee-Chung LU
  • Publication number: 20240092662
    Abstract: A method for removing a heavy metal from water includes subjecting a microbial solution containing a liquid culture of a urease-producing bacterial strain and a reaction solution containing a manganese compound and urea to a microbial-induced precipitation reaction, so as to obtain biomineralized manganese carbonate (MnCO3) particles, admixing the biomineralized MnCO3 particles with water containing a heavy metal, so that the biomineralized MnCO3 particles adsorb the heavy metal in the water to form a precipitate, and removing the precipitate from the water.
    Type: Application
    Filed: February 9, 2023
    Publication date: March 21, 2024
    Inventors: Chien-Yen CHEN, Yi-Hsun HUANG, Pin-Yun LIN, Anggraeni Kumala DEWI, Koyeli DAS, Uttara SUKUL, Tsung-Hsien CHEN, Raju Kumar SHARMA, Cheng-Kang LU, Chung-Ming LU
  • Publication number: 20240095774
    Abstract: A search engine coupled to a database of product information is provided a search query having a datapoint and the search engine uses at least the datapoint to generate a search result. A vendor system associated with the search engine subsequently uses one or more interactions with the generated search result to update a conversion value that is linked within a datastore of the vendor system to the datapoint. When it is determined by the vendor system that the updated conversion value that is linked within the datastore to the datapoint was caused to exceed a predetermined threshold value, the vendor system causes a notification to be sent to one or more consumers that previously provided the datapoint for use in a search by the search engine.
    Type: Application
    Filed: August 25, 2023
    Publication date: March 21, 2024
    Inventors: Jean-Marc Francois Reynaud, Geoffry A. Westphal, Thomas Allen Mathis, Immanuel Savio Donbosco, Yen-Chen Chou
  • Publication number: 20240099150
    Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
  • Publication number: 20240098833
    Abstract: A method for mobility enhancement in wireless communication systems is provided. The method is performed by a User Equipment (UE) configured with a first Small Data Transmission (SDT) configuration by a first cell. The method includes receiving a Radio Resource Control (RRC) release message including a suspend configuration from the first cell; transitioning to an RRC INACTIVE state in response to receiving the RRC release message; receiving, in the RRC INACTIVE state, a System Information Block Type 1 (SIB1) including a second SDT configuration from a second cell; camping on the second cell in response to receiving the SIB1 from the second cell; and while the UE is camping on the second cell, refraining from using the first SDT configuration to initiate an SDT procedure associated with the second cell in a case that the UE does not support performing the SDT procedure associated with the second cell.
    Type: Application
    Filed: September 14, 2023
    Publication date: March 21, 2024
    Inventors: YUNG-LAN TSENG, YEN-HUA LI, HAI-HAN WANG, HUNG-CHEN CHEN
  • Publication number: 20240098959
    Abstract: A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 21, 2024
    Inventors: Kai-Hsuan Lee, Chia-Ta Yu, Cheng-Yu Yang, Sheng-Chen Wang, Sai-Hooi Yeong, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 11935859
    Abstract: A chip structure includes a first substrate, a second substrate, a conductive via, and a redistribution layer. The first substrate has a first inclined sidewall. The second substrate is located on a bottom surface of the first substrate, and has an upper portion and a lower portion. The lower portion extends from the upper portion. The upper portion is between the first substrate and the lower portion. The upper portion has a second inclined sidewall, and a slope of the first inclined sidewall is substantially equal to a slope of the second inclined sidewall. The conductive via is in the lower portion. The redistribution layer extends from a top surface of the first substrate to a top surface of the lower portion of the second substrate sequentially along the first inclined sidewall and the second inclined sidewall, and is electrically connected to the conductive via.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: March 19, 2024
    Assignee: XINTEC INC.
    Inventors: Jiun-Yen Lai, Chia-Hsiang Chen
  • Patent number: 11935783
    Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yen Huang, Shao-Kuan Lee, Cheng-Chin Lee, Hai-Ching Chen, Shau-Lin Shue
  • Publication number: 20240088025
    Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 14, 2024
    Inventors: Hsin-Yen Huang, Kai-Fang Cheng, Chi-Lin Teng, Hai-Ching Chen, Tien-I Bao
  • Publication number: 20240083828
    Abstract: The present application relates to a system and a method for producing vinyl chloride. The system comprise a preheat unit, a gas-liquid separating unit, a heat-recovery unit, a heating unit and a thermal pyrolysis unit, and therefore heat energy of the thermal pyrolysis product can be efficiently recovered. Energy cost of the system can be efficiently lowered with the heat-recovery unit and the heating unit, and further prolonging operating cycle of the system.
    Type: Application
    Filed: June 28, 2023
    Publication date: March 14, 2024
    Inventors: Wen-Hsi HUANG, Sheng-Yen KO, Shih-Hong CHEN, Chun-Yu LIN
  • Publication number: 20240088225
    Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.
    Type: Application
    Filed: November 14, 2023
    Publication date: March 14, 2024
    Inventors: Su-Hao Liu, Wen-Yen Chen, Li-Heng Chen, Li-Ting Wang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Ying-Lang Wang
  • Patent number: 11929333
    Abstract: An integrated fan-out (InFO) package includes a die, an encapsulant, a redistribution structure, a slot antenna, an insulating layer, a plurality of conductive structures, and an antenna confinement structure. The encapsulant laterally encapsulates the die. The redistribution structure is disposed on the die and the encapsulant. The slot antenna is disposed above the redistribution structure. The insulating layer is sandwiched between the redistribution structure and the slot antenna. The conductive structures and the antenna confinement structure extend from the slot antenna to the redistribution structure.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Tzu-Chun Tang, Chieh-Yen Chen, Che-Wei Hsu
  • Publication number: 20240079558
    Abstract: A method of manufacturing a positive electrode material has the steps of synthesizing an iron metal in a phosphoric acid solution to form an iron phosphate dispersion solution; adding a vanadium pentoxide (V2O5), a non-ionic surfactant and a carbon source to the iron phosphate dispersion solution; and adding a lithium salt to the iron phosphate dispersion solution and then grinding and dispersing it to produce a positive electrode material. By regulating the timing of the addition of vanadium pentoxide (V2O5), the present invention enables the battery made of the positive electrode material to have the advantage of higher battery performance.
    Type: Application
    Filed: June 21, 2023
    Publication date: March 7, 2024
    Inventors: Chao-Nan Wei, Feng-Yen Tsai, Ya-Hui Wang, Han-Yu Chen
  • Publication number: 20240079767
    Abstract: An antenna module is provided. The antenna module includes a dielectric substrate, a radio frequency integrated circuit (RFIC) and a first number of first antennas. The radio frequency integrated circuit (RFIC) is disposed on the dielectric substrate, wherein the RFIC comprises a single first antenna port group and second antenna port groups to receive or transmit signals. The first number of first antennas is arranged in a first row on the dielectric substrate, wherein at least two of the first antennas are connected to the first antenna port group of the RFIC.
    Type: Application
    Filed: August 24, 2023
    Publication date: March 7, 2024
    Inventors: Yen-Ju LIN, Wun-Jian LIN, Shih-Huang YEH, Nai-Chen LIU
  • Publication number: 20240079392
    Abstract: A semiconductor structure includes a first tier, a redistribution circuit structure, and a second tier. The first tier includes at least one first die. The redistribution circuit structure is disposed on the first tier and electrically coupled to the at least one first die, where the redistribution circuit structure has a multi-layer structure and includes a vertical connection structure continuously extending from a first side of the redistribution circuit structure to a second side of the redistribution circuit structure, and the first side is opposite to the second side along a stacking direction of the first tier and the redistribution circuit structure. The second tier includes a plurality of second dies, and is disposed on and electrically coupled to the redistribution circuit structure.
    Type: Application
    Filed: January 10, 2023
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang WANG, Tso-Jung Chang, Jeng-Shien Hsieh, Shih-Ping Lin, Chih-Peng Lin, Chieh-Yen Chen, Chen-Hua Yu
  • Patent number: D1018147
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: March 19, 2024
    Assignee: MillerKnoll, Inc.
    Inventors: Hung-Ming Chen, Chen-Yen Wei