Patents by Inventor Yen Cheng Chen

Yen Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10714394
    Abstract: A method of forming a fin field effect transistor (finFET) on a substrate includes forming a fin structure on the substrate and forming a shallow trench isolation (STI) region on the substrate. First and second fin portions of the fin structure extend above a top surface of the STI region. The method further includes oxidizing the first fin portion to convert a first material of the first fin portion to a second material. The second material is different from the first material of the first fin portion and a material of the second fin portion. The method further includes forming an oxide layer on the oxidized first fin portion and the second fin portion and forming first and second polysilicon structures on the oxide layer.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Kuan-Lun Cheng, Yen-Ming Chen
  • Patent number: 10714619
    Abstract: A method for fabricating a semiconductor device includes forming a doped semiconductor layer on a substrate and forming a fin structure disposed on the doped semiconductor layer. The fin structure is doped with a p-type dopant. The method further includes forming a source/drain region within an upper portion of the fin structure and forming a fin sidewall along a lower portion of the fin structure. The fin sidewall has the p-type dopant.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Wei-Yang Lee, Chia-Chun Lan, Chia-Ling Chan, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20200217715
    Abstract: A photodetecting device for detecting different wavelengths includes a first photodetecting component including a substrate and a second photodetecting component including second absorption region. The substrate includes a first absorption region configured to absorb photons having a first peak wavelength and to generate first photo-carriers. The second absorption region is supported by the substrate and configured to absorb photons having a second peak wavelength and to generate second photo-carriers. The first absorption region and the second absorption region are overlapped along a vertical direction.
    Type: Application
    Filed: January 6, 2020
    Publication date: July 9, 2020
    Inventors: YEN-CHENG LU, YUN-CHUNG NA, SHU-LU CHEN, CHIEN-YU CHEN, SZU-LIN CHENG, CHUNG-CHIH LIN, YU-HSUAN LIU
  • Patent number: 10705639
    Abstract: An anti-reflective integrated touch display panel includes an anti-reflective structure and touch electrodes. The anti-reflective structure includes a first insulating layer, a second insulating layer disposed on the first insulating layer, a conducting layer disposed on the second insulating layer, a third insulating layer disposed on the second insulating layer, and a fourth insulating layer disposed on the third insulating layer. The first insulating layer includes silicon oxide or silicon nitride, and has a thickness of 0.1 to 2 micrometers. The second insulating layer includes silicon oxide or strontium oxide, and has a thickness of 0.001 to 0.1 micrometer. The conducting layer includes molybdenum, and has a thickness of 0.01 to 0.05 micrometer. The fourth insulating layer includes silicon nitride, and has a thickness of 0.001 to 0.3 micrometer. The touch electrodes are disposed between the third insulating layer and the fourth insulating layer.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: July 7, 2020
    Assignee: Au Optronics Corporation
    Inventors: Chun-Cheng Hung, Wen-Jen Li, Yen-Shih Huang, Chia-Ming Chen, Ting-Wei Ko, Chia-Yuan Yeh
  • Publication number: 20200212244
    Abstract: A photodetector includes: a substrate; a first semiconductor region, the first semiconductor region extending into the substrate from a front side of the substrate; and a second semiconductor region, the second semiconductor region further extending into the substrate from a bottom boundary of the first semiconductor region, wherein when the photodetector operates under a Geiger mode, the second semiconductor region is fully depleted to absorb a radiation source received from a back side of the substrate.
    Type: Application
    Filed: March 13, 2020
    Publication date: July 2, 2020
    Inventors: Chia-Yu WEI, Yu-Ting KAO, Yen-Liang LIN, Wen-I HSU, Hsun-Ying HUANG, Kuo-Cheng LEE, Hsin-Chi CHEN
  • Publication number: 20200200528
    Abstract: A measuring program compiling device and a measuring program compiling method thereof are provided. The method includes analyzing a first measuring program to obtain a plurality of first measuring parameters corresponding to the first measuring program, and converting the first measuring parameters into a plurality of second measuring parameters corresponding to a plurality of planning operations; generating a plurality of standardized measuring parameters according to the second measuring parameters and a plurality of computer aided design (CAD) image parameters; receiving a plurality of parameter input operations corresponding to the planning operations to update the second measuring parameters; generating a standardized measuring program corresponding to a CAD file according to the standardized measuring parameters; and converting the standardized measuring program into a target measuring program executed on a target measuring device according to specification data of the target measuring device.
    Type: Application
    Filed: April 17, 2019
    Publication date: June 25, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: Kai-Ming Pan, Ta-Jen Peng, Yen-Cheng Chen, Qi-Zheng Yang, Chen-Yu Kai
  • Patent number: 10691014
    Abstract: A lithography system includes a radiation source configured to generate an extreme ultraviolet (EUV) light. The lithography system includes a mask that defines one or more features of an integrated circuit (IC). The lithography system includes an illuminator configured to direct the EUV light onto the mask. The mask diffracts the EUV light into a 0-th order ray and a plurality of higher order rays. The lithography system includes a wafer stage configured to secure a wafer that is to be patterned according to the one or more features defined by the mask. The lithography system includes a pupil phase modulator positioned in a pupil plane that is located between the mask and the wafer stage. The pupil phase modulator is configured to change a phase of the 0-th order ray.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: June 23, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Cheng Lu, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Publication number: 20200192032
    Abstract: A photo-detecting apparatus includes an optical-to-electric converter, having a first output terminal, configured to convert an incident light to an electrical signal; a cascode transistor, having a control terminal, a first channel terminal and a second channel terminal, wherein the second channel terminal of the cascode transistor is coupled to the first output terminal of the optical-to-electric converter; and a reset transistor, having a control terminal, a first channel terminal and a second channel terminal, wherein the first channel terminal of the reset transistor is coupled to a supply voltage and the second channel terminal of the reset transistor is coupled to the first channel terminal of the cascode transistor.
    Type: Application
    Filed: December 6, 2019
    Publication date: June 18, 2020
    Inventors: Yun-Chung Na, Che-Fu Liang, Chien-Lung Chen, Yuan-Fu Lyu, Yen-Cheng Lu
  • Patent number: 10684552
    Abstract: Various methods are disclosed herein for reducing (or eliminating) printability of mask defects during lithography processes. An exemplary method includes performing a first lithography exposing process and a second lithography exposing process using a mask to respectively image a first set of polygons oriented substantially along a first direction and a second set of polygons oriented substantially along a second direction on a target. During the first lithography exposing process, a phase distribution of light diffracted from the mask is dynamically modulated to defocus any mask defect oriented at least partially along both the first direction and a third direction that is different than the first direction. During the second lithography exposing process, the phase distribution of light diffracted from the mask is dynamically modulated to defocus any mask defect oriented at least partially along both the second direction and a fourth direction that is different than the third direction.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Cheng Lu, Chia-Hao Hsu, Shinn-Sheng Yu, Chia-Chen Chen, Jeng-Horng Chen, Anthony Yen
  • Patent number: 10685704
    Abstract: A static random access memory (SRAM) includes a bit cell that includes a p-type pass gate, a bit information path connected to the bit cell by the p-type pass gate, and a write multiplexer connected to the bit information path. The write multiplexer includes a p-type transistor configured to selectively couple the bit information path to a flip-flop.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Cheng Wu, Wei Min Chan, Yen-Huei Chen, Hung-Jen Liao, Ping-Wei Wang
  • Patent number: 10684009
    Abstract: An apparatus coupled to a chamber for processing extreme ultraviolet radiation includes a gas inlet configured to direct exhaust gases from the chamber into a combustion zone. The combustion zone is configured to flamelessly ignite the exhaust gases. An air inlet is configured to direct a mixture of air and a fuel into the combustion zone. A control valve is configured to change a volume of fluid exhausted from the combustion zone. A controller configured to control the control valve so as to prevent a pressure inside the combustion zone from exceeding a preset pressure value is provided.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Hsun Tsai, Ping-Cheng Li, Yen-Hsun Chen
  • Publication number: 20200185440
    Abstract: A gate structure includes a gate and a first isolation structure having a top surface and a bottom surface. The gate includes a first sidewall adjacent to the first isolation structure, a second sidewall, a first horizontal surface adjacent to a bottom edge of the first sidewall and a bottom edge of the second sidewall, the first horizontal surface being between the top surface of the first isolation structure and the bottom surface of the first isolation structure. The gate also includes a second horizontal surface adjacent to a top edge of the second sidewall. An effective channel width defined by the gate structure includes a height of the second sidewall and a width of the second horizontal surface.
    Type: Application
    Filed: February 13, 2020
    Publication date: June 11, 2020
    Inventors: Chia-Yu WEI, Fu-Cheng CHANG, Hsin-Chi CHEN, Ching-Hung KAO, Chia-Pin CHENG, Kuo-Cheng LEE, Hsun-Ying HUANG, Yen-Liang LIN
  • Patent number: 10680727
    Abstract: An over-the-air (OTA) wireless test system includes a container, a machine plate disposed on the container, a supporter disposed on the machine plate, a load board disposed on the supporter, a socket disposed on the load board, a device under test (DUT) installed in the socket, and a wave-guiding feature in the socket and the load board configured to pass and guide electromagnetic waves to and/or from an antenna structure of the DUT. The wave-guiding feature comprises a wave-guiding channel in the socket defined by a plurality of pogo pins surrounding the antenna structure of the DUT. The wave-guiding feature may further comprise a radiation passage in the load board defined by rows of via fence extending through an entire thickness of the load board.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: June 9, 2020
    Assignee: MediaTek Inc.
    Inventors: Yen-Ju Lu, Chih-Ming Hung, Wen-Chou Wu, Nan-Cheng Chen
  • Publication number: 20200176591
    Abstract: In an embodiment, a method includes: forming a fin extending from a substrate, the fin having a first width and a first height after the forming; forming a dummy gate stack over a channel region of the fin; growing an epitaxial source/drain in the fin adjacent the channel region; and after growing the epitaxial source/drain, replacing the dummy gate stack with a metal gate stack, the channel region of the fin having the first width and the first height before the replacing, the channel region of the fin having a second width and a second height after the replacing, the second width being less than the first width, the second height being less than the first height.
    Type: Application
    Filed: April 12, 2019
    Publication date: June 4, 2020
    Inventors: I-Hsieh Wong, Yen-Ting Chen, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 10672776
    Abstract: A memory circuit including: a first column of memory cells, each memory cell of the first column including a first supply segment; a first supply voltage line in a first conductive layer, the first supply voltage line being made of at least the first supply segments of the first column; a second supply voltage line; a first resistive device electrically connecting the first and second supply voltage lines, and being located in a via layer; a first material, from which the first resistive device is formed, being different than a second material from which a first type of via plug in the via layer is formed; and a supply voltage source electrically coupled with first supply voltage line through one or more conductive paths, and the second supply voltage line and the first resistive device being in a lowest resistance path of the one or more conductive paths.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Huei Chen, Hung-Jen Liao, Chih-Yu Lin, Jonathan Tsung-Yung Chang, Wei-Cheng Wu
  • Publication number: 20200168735
    Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. An exemplary semiconductor device comprises a fin disposed over a substrate, wherein the fin includes a channel region and a source/drain region; a gate structure disposed over the substrate and over the channel region of the fin; a source/drain feature epitaxially grown in the source/drain region of the fin, wherein the source/drain feature includes a top epitaxial layer and a lower epitaxial layer formed below the top epitaxial layer, and the lower epitaxial layer includes a wavy top surface; and a contact having a wavy bottom surface matingly engaged with the wavy top surface of the lower epitaxial layer of the source/drain feature..
    Type: Application
    Filed: October 18, 2019
    Publication date: May 28, 2020
    Inventors: Chia-Ta Yu, Yen-Chieh Huang, Wei-Yuan Lu, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20200167073
    Abstract: A computer system, operated on a system platform, includes memories and a controller circuit. The memories include a first memory and a second memory, in which the first memory include s a first storage space and a second storage space, and a size of a total storage space of the second memory is the same as a size of the first storage space. The memories are coupled in parallel with the controller circuit, and the controller circuit assigns at least one first data zone to the first storage space and the second memory based on a kernel of the system platform, and assigns a second data zone to the second storage space. A data access frequency of the second data zone is lower than a data access frequency of the at least one first data zone.
    Type: Application
    Filed: May 28, 2019
    Publication date: May 28, 2020
    Inventors: Yi-Cheng CHEN, Yen-Fu LAI, Kun-Wei WANG
  • Publication number: 20200168723
    Abstract: A semiconductor device includes first and second semiconductor fins extending from a substrate and a source/drain region epitaxially grown in recesses of the first and second semiconductor fins. A top surface of the source/drain region is higher than a surface level with top surfaces of the first and second semiconductor fins. The source/drain region includes a plurality of buffer layers. Respective layers of the plurality of buffer layers are embedded between respective layers of the source/drain region. Each of the plurality of buffer layers may have an average thickness in a range of about 2 ? to about 30 ?.
    Type: Application
    Filed: November 13, 2019
    Publication date: May 28, 2020
    Inventors: Tzu-Hsiang Hsu, Ting-Yeh Chen, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20200161297
    Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. A top portion of the semiconductor fin is formed of a first semiconductor material. A semiconductor cap layer is formed on a top surface and sidewalls of the semiconductor fin. The semiconductor cap layer is formed of a second semiconductor material different from the first semiconductor material. The method further includes forming a gate stack on the semiconductor cap layer, forming a gate spacer on a sidewall of the gate stack, etching a portion of the semiconductor fin on a side of the gate stack to form a first recess extending into the semiconductor fin, recessing the semiconductor cap layer to form a second recess directly underlying a portion of the gate spacer, and performing an epitaxy to grow an epitaxy region extending into both the first recess and the second recess.
    Type: Application
    Filed: June 3, 2019
    Publication date: May 21, 2020
    Inventors: Yen-Ting Chen, Bo-Yu Lai, Chien-Wei Lee, Hsueh-Chang Sung, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 10658184
    Abstract: A method for semiconductor manufacturing includes providing a substrate and a patterning layer over the substrate; forming a hole in the patterning layer; applying a first directional etching along a first direction to inner sidewalls of the hole; and applying a second directional etching along a second direction to the inner sidewalls of the hole, wherein the second direction is different from the first direction.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Tien Shen, Chi-Cheng Hung, Chin-Hsiang Lin, Chien-Wei Wang, Ching-Yu Chang, Chih-Yuan Ting, Kuei-Shun Chen, Ru-Gun Liu, Wei-Liang Lin, Ya Hui Chang, Yuan-Hsiang Lung, Yen-Ming Chen, Yung-Sung Yen