Patents by Inventor Yen-Chieh Chen

Yen-Chieh Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210013301
    Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a substrate, and the substrate includes a capacitor region and a non-capacitor region. The MIM capacitor structure includes a first electrode layer formed over the substrate, and a first spacer formed on a sidewall of the first electrode layer. The MIM capacitor structure includes a second electrode layer formed over the first electrode layer, and a second spacer formed on a sidewall of the second electrode layer. The second spacer is in direct contact with an interface between the second electrode layer and a first dielectric layer.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Inventors: Chih-Fan HUANG, Chih-Yang PAI, Yuan-Yang HSIAO, Tsung-Chieh HSIAO, Hui-Chi CHEN, Dian-Hau CHEN, Yen-Ming CHEN
  • Publication number: 20210004694
    Abstract: An IoT system includes a computing module for controlling an integral function of the system and including an analysis unit and a machine learning unit. The analysis unit is capable of operational analysis and creating a predictive model and creating a predictive model according to the data analyzed. The machine learning unit has an algorithm function to create a corresponding learning model. An IoT module is electrically connected to the computing module to serve as an intermediate role. At least one detection unit is electrically connected to the IoT module and disposed in soil to detect data of environmental and soil conditions and sends the data detected to the computing module for subsequent analysis.
    Type: Application
    Filed: October 20, 2019
    Publication date: January 7, 2021
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Wen-Liang Chen, Lung-Chieh Chen, Szu-Chia Chen, Wei-Han Chen, Chun-Yu Chu, Yu-Chi Shih, Yu-Ci Chang, Tzu-I Hsieh, Yen-Ling Chen, Li-Chi Peng, Meng-Zhan Lee, Jui-Yu Ho, Chi-Yao Ku, Nian-Ruei Deng, Yuan-Yao Chan, Erick Wang, Tai-Hsiang Yen, Shao-Yu Chiu, Jiun-Yi Lin, Yun-Wei Lin, Fung Ling Ng, Yi-Bing Lin, Chin-Cheng Wang
  • Publication number: 20200371425
    Abstract: In a method of manufacturing a photo mask, a resist layer is formed over a mask blank, which includes a mask substrate, a phase shift layer disposed on the mask substrate and a light blocking layer disposed on the phase shift layer. A resist pattern is formed by using a lithographic operation. The light blocking layer is patterned by using the resist pattern as an etching mask. The phase shift layer is patterned by using the patterned light blocking layer as an etching mask. A border region of the mask substrate is covered with an etching hard cover, while a pattern region of the mask substrate is opened. The patterned light blocking layer in the pattern region is patterned through the opening of the etching hard cover. A photo-etching operation is performed on the pattern region to remove residues of the light blocking layer.
    Type: Application
    Filed: August 10, 2020
    Publication date: November 26, 2020
    Inventors: Chun-Chieh TIEN, Cheng-Hsuen CHIANG, Chih-Ming CHEN, Cheng-Ming LIN, Yen-Wei HUANG, Hao-Ming CHANG, Kuo-Chin LIN, Kuan-Shien LEE
  • Publication number: 20200365683
    Abstract: The present disclosure is directed to a method of fabrication a semiconductor structure. The method includes providing a substrate and forming a bottom electrode over the substrate, wherein a terminal end of the bottom electrode has a tapered sidewall. The method also includes depositing an insulating layer over the bottom electrode and forming a top electrode over the insulating layer, wherein a terminal end of the top electrode has a vertical sidewall.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 19, 2020
    Inventors: Chih-Fan Huang, Hung-Chao Kao, Yuan-Yang Hsiao, Tsung-Chieh Hsiao, Hsiang-Ku Shen, Hui-Chi Chen, Dian-Hau Chen, Yen-Ming Chen
  • Patent number: 10811318
    Abstract: A fin field effect transistor (FinFET) device structure with dummy fin structures and method for forming the same are provided. The FinFET device structure includes an isolation structure over a substrate, and a first fin structure extended above the isolation structure. The FinFET device structure includes a second fin structure embedded in the isolation structure, and a liner layer formed on sidewalls of the first fin structures and sidewalls of the second fin structures. The FinFET device structure includes a material layer formed over the second fin structures, and the material layer and the isolation structure are made of different materials.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzung-Yi Tsai, Yen-Ming Chen, Tsung-Lin Lee, Chih-Chieh Yeh
  • Patent number: 10739671
    Abstract: In a method of manufacturing a photo mask, a resist layer is formed over a mask blank, which includes a mask substrate, a phase shift layer disposed on the mask substrate and a light blocking layer disposed on the phase shift layer. A resist pattern is formed by using a lithographic operation. The light blocking layer is patterned by using the resist pattern as an etching mask. The phase shift layer is patterned by using the patterned light blocking layer as an etching mask. A border region of the mask substrate is covered with an etching hard cover, while a pattern region of the mask substrate is opened. The patterned light blocking layer in the pattern region is patterned through the opening of the etching hard cover. A photo-etching operation is performed on the pattern region to remove residues of the light blocking layer.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh Tien, Cheng-Hsuen Chiang, Chih-Ming Chen, Cheng-Ming Lin, Yen-Wei Huang, Hao-Ming Chang, Kuo Chin Lin, Kuan-Shien Lee
  • Patent number: 10732725
    Abstract: A method of interactive display based on gesture recognition includes determining a plurality of gestures corresponding to a plurality of images, interpreting a predetermined combination of gestures among the plurality of gestures as a command, and displaying a scene in response to the command.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: August 4, 2020
    Assignee: XRSpace CO., LTD.
    Inventors: Peter Chou, Feng-Seng Chu, Yen-Hung Lin, Shih-Hao Ke, Jui-Chieh Chen
  • Patent number: 10734474
    Abstract: A metal-insulator-metal (MIM) capacitor structure includes a semiconductor substrate and a bottom conductive layer above the semiconductor substrate. The bottom conductive layer has a slanted sidewall with respect to a top surface of the semiconductor substrate. The MIM capacitor structure further includes a top conductive layer above the bottom conductive layer. The top conductive layer has a vertical sidewall with respect to the top surface of the semiconductor substrate. The MIM capacitor structure further includes an insulating layer interposed between the bottom conductive layer and the top conductive layer. The insulating layer covers the slanted sidewall of the bottom conductive layer.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Fan Huang, Hung-Chao Kao, Yuan-Yang Hsiao, Tsung-Chieh Hsiao, Hsiang-Ku Shen, Hui-Chi Chen, Dian-Hau Chen, Yen-Ming Chen
  • Patent number: 10718635
    Abstract: A contact detection circuit is applied to a four-terminal measurement device. The contact detection circuit comprises a first isolator, a signal generator, a multiplier and a calculator. The first isolator comprises a primary side and a secondary side, with the secondary side comprising a first terminal and a second terminal, with the first terminal configured to be electrically connected to a driving terminal and the second terminal configured to be electrically connected to a measuring terminal. The signal generator is configured to provide a measuring signal. The multiplier is configured to generate an output signal based on the measuring signal and a first reflected signal when the first reflected signal is induced at the primary side of the first isolator based on the measuring signal. The calculator calculates contact resistance between the driving terminal and the measuring terminal based on a direct-current component of the output signal.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: July 21, 2020
    Assignee: CHROMA ATE INC.
    Inventors: Tsz-Lang Chen, Ming-Chieh Lin, Yen-Ching Liu
  • Patent number: 10693950
    Abstract: A control method for network communication system including base station network management server comprises of obtaining an item of neighbor base station identification information of a neighbor base station by a first base station; providing the first base station identification information to a base station network management server by the first base station; obtaining a first base station neighbor information from the base station network management server by a first MEC platform; producing an item of first platform neighbor information by the first MEC platform; determining whether a request signal matches the first platform neighbor information after receiving the request signal from a second MEC platform; providing the first platform identification information to the second MEC platform while determining that the request signal matches the first platform neighbor information.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: June 23, 2020
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yen-Chiu Chen, Chun-Chieh Wang
  • Patent number: 10678342
    Abstract: A method of virtual user interface interaction based on gesture recognition comprises detecting two hands in a plurality of images, recognizing each hand's gesture, projecting a virtual user interface on an open gesture hand when one hand is recognized with a point gesture and the other hand is recognized with an open gesture, tracking an index fingertip of the point gesture hand, determining whether the index fingertip of the point gesture hand is close to the open gesture hand within a predefined rule, interpreting a movement of the index fingertip of the point gesture hand as a click command when the index fingertip of the point gesture hand is close to the open gesture hand within the predefined rule, and in response to the click command, generating image data with a character object of the virtual user interface object.
    Type: Grant
    Filed: October 21, 2018
    Date of Patent: June 9, 2020
    Assignee: XRSpace CO., LTD.
    Inventors: Peter Chou, Feng-Seng Chu, Yen-Hung Lin, Shih-Hao Ke, Jui-Chieh Chen
  • Publication number: 20200176306
    Abstract: Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.
    Type: Application
    Filed: August 21, 2019
    Publication date: June 4, 2020
    Inventors: Yu-Hung Cheng, Pu-Fang Chen, Cheng-Ta Wu, Po-Jung Chiang, Ru-Liang Lee, Victor Y. Lu, Yen-Hsiu Chen, Yeur-Luen Tu, Yu-Lung Yeh, Shi-Chieh Lin
  • Publication number: 20200168735
    Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. An exemplary semiconductor device comprises a fin disposed over a substrate, wherein the fin includes a channel region and a source/drain region; a gate structure disposed over the substrate and over the channel region of the fin; a source/drain feature epitaxially grown in the source/drain region of the fin, wherein the source/drain feature includes a top epitaxial layer and a lower epitaxial layer formed below the top epitaxial layer, and the lower epitaxial layer includes a wavy top surface; and a contact having a wavy bottom surface matingly engaged with the wavy top surface of the lower epitaxial layer of the source/drain feature..
    Type: Application
    Filed: October 18, 2019
    Publication date: May 28, 2020
    Inventors: Chia-Ta Yu, Yen-Chieh Huang, Wei-Yuan Lu, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20200144126
    Abstract: A fin field effect transistor (FinFET) device structure with dummy fin structures and method for forming the same are provided. The FinFET device structure includes an isolation structure over a substrate, and a first fin structure extended above the isolation structure. The FinFET device structure includes a second fin structure embedded in the isolation structure, and a liner layer formed on sidewalls of the first fin structures and sidewalls of the second fin structures. The FinFET device structure includes a material layer formed over the second fin structures, and the material layer and the isolation structure are made of different materials.
    Type: Application
    Filed: December 30, 2019
    Publication date: May 7, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tzung-Yi TSAI, Yen-Ming CHEN, Tsung-Lin LEE, Chih-Chieh YEH
  • Publication number: 20200130138
    Abstract: Provided herein are chemical-mechanical planarization (CMP) systems and methods to reduce metal particle pollution on dressing disks and polishing pads. Such methods may include contacting a dressing disk and at least one conductive element with an electrolyte solution and applying direct current (DC) power to the dressing disk and the at least one conductive element.
    Type: Application
    Filed: September 26, 2019
    Publication date: April 30, 2020
    Inventors: Chih-Chieh CHANG, Yen-Ting CHEN, Hui-Chi HUANG, Kei-Wei CHEN
  • Publication number: 20200135538
    Abstract: In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a chemical mechanical polishing (CMP) stop layer is formed over the first ILD layer, a trench is formed by patterning the CMP stop layer and the first ILD layer, a metal layer is formed over the CMP stop layer and in the trench, a sacrificial layer is formed over the metal layer, a CMP operation is performed on the sacrificial layer and the metal layer to remove a portion of the metal layer over the CMP stop layer, and a remaining portion of the sacrificial layer over the trench is removed.
    Type: Application
    Filed: September 26, 2019
    Publication date: April 30, 2020
    Inventors: Tsai-Ming HUANG, Wei-Chieh HUANG, Hsun-Chung KUANG, Yen-Chang CHU, Cheng-Che CHUNG, Chin-Wei LIANG, Ching-Sen KUO, Jieh-Jang CHEN, Feng-Jia SHIU, Sheng-Chau CHEN
  • Patent number: 10635252
    Abstract: A touch module includes a substrate and a touch electrode layer. The touch electrode layer is disposed on the substrate. The touch electrode layer includes a plurality of main mesh patterns and a plurality of dummy mesh patterns. The dummy mesh patterns of the touch electrode layer each have a plurality of breakpoints.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: April 28, 2020
    Assignees: INTERFACE TECHNOLOGY (CHENGDU) CO., LTD., INTERFACE OPTOELECTRONICS (SHENZHEN) CO., LTD., GENERAL INTEFACE SOLUTION LIMITED
    Inventors: Hung-Chieh Chin, Yueh-Feng Yang, Po-Lin Chen, Yen-Heng Huang, Ju-Xiang Liu
  • Publication number: 20200125176
    Abstract: A method of virtual user interface interaction based on gesture recognition comprises detecting two hands in a plurality of images, recognizing each hand's gesture, projecting a virtual user interface on an open gesture hand when one hand is recognized with a point gesture and the other hand is recognized with an open gesture, tracking an index fingertip of the point gesture hand, determining whether the index fingertip of the point gesture hand is close to the open gesture hand within a predefined rule, interpreting a movement of the index fingertip of the point gesture hand as a click command when the index fingertip of the point gesture hand is close to the open gesture hand within the predefined rule, and in response to the click command, generating image data with a character object of the virtual user interface object.
    Type: Application
    Filed: October 21, 2018
    Publication date: April 23, 2020
    Inventors: Peter Chou, Feng-Seng Chu, Yen-Hung Lin, Shih-Hao Ke, Jui-Chieh Chen
  • Patent number: 10626499
    Abstract: A deposition device structure is provided. The deposition device structure includes a heater in a chamber. The deposition device structure also includes a shower head over the heater. The shower head includes holes extending from a top surface of the shower head to a bottom surface of the shower head. The bottom surface of the shower head faces the heater. The bottom surface of the shower head has a first section and a second section. The second section of the bottom surface is rougher than the first section of the bottom surface.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: April 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Chan Lo, Huan-Chieh Chen, Yi-Fang Lai, Keith Kuang-Kuo Koai, Chin-Feng Sun, Po-Hsiung Leu, Ding-I Liu, Kai-Shiung Hsu
  • Patent number: 10607848
    Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A substrate is provided. A material layer having an opening is formed on the substrate. A first passivation material layer is formed on sidewalls of the opening and on the substrate. A treatment process is performed to the first passivation material layer to form a second passivation material layer. A first surface of the second passivation material layer and a second surface (at an inner side) of the second passivation material layer are differ in a property, and the first surface is located at a side of the second passivation material layer relatively away from the material layer.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: March 31, 2020
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Yuan-Chieh Chiu, Shih-Ping Hong, Kuang-Chao Chen, Yen-Ju Chen