Patents by Inventor Yen-Di Tsen

Yen-Di Tsen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190375071
    Abstract: An apparatus for CMP includes a wafer carrier retaining a semiconductor wafer during a polishing operation, a slurry dispenser dispensing an abrasive slurry, and a temperature control system monitoring and controlling a temperature variation during the polishing operation. The temperature control system includes a temperature sensor detecting a temperature during the polishing operation and providing a signal corresponding to the temperature, a temperature controller coupled to the temperature sensor and receiving the signal from the temperature sensor, and a cooling device coupled to the temperature controller and providing a coolant to the apparatus for CMP.
    Type: Application
    Filed: June 8, 2018
    Publication date: December 12, 2019
    Inventors: HE HUI PENG, JAMES JENG-JYI HWANG, CHI-MING YANG, YUNG-YAO LEE, YEN-DI TSEN
  • Patent number: 10096482
    Abstract: An apparatus and method for providing target thickness and surface profile uniformity control of a multi-head chemical mechanical polishing (CMP) process is disclosed. An exemplary method includes providing at least two wafers; determining a surface profile of each of the at least two wafers; determining an operation mode for a chemical mechanical polishing (CMP) process based on the surface profiles of the at least two wafers; determining a CMP polishing recipe for each of the at least two wafers based on the operation mode; and performing the CMP process on the at least two wafers based on the determined CMP polishing recipes.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: October 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Keung Hui, Jin-Ning Sung, Jong-I Mou, Soon-Kang Huang, Yen-Di Tsen
  • Patent number: 9997420
    Abstract: One or more methods or systems for performing chemical mechanical planarization (CMP) are provided. The system includes at least one of an emitter, a detector, a spectroscopic signal generator, a comparator, a spectral library, a controller or a CMP device. A spectroscopic signal is generated and is used to determine the thickness of a first material formed on or from a wafer by comparing the spectroscopic signal to a spectral library. Responsive to the thickness not being equal to the desired thickness, the controller instructs the CMP device to perform a rotation to reduce the thickness of the first material. The system and method herein increase the sensitivity of the CMP, such that the thickness of the first material is reduced with greater accuracy and precision, as compared to where the thickness is not measured between consecutive rotations of a wafer.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: June 12, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yen-Di Tsen, Cheng Yen-Wei, Jong-I Mou
  • Patent number: 9733577
    Abstract: In some embodiments, the present application is directed to a method and system for process control of a lithography tool. The method transfers a reference pattern to exposure fields of a reference workpiece to form pairs of overlapping reference layers. Misalignment between the overlapping reference layers is measured to form first and second baseline maps, and a ? baseline map is formed from the first and second baseline maps. A production pattern is transferred to exposure fields of a production workpiece to form second production layers arranged over and aligned to first production layers. Misalignment between the first and second production layers is measured to form a production map. The ? baseline map is transformed and subsequently added to the production map, to form a final production map. Parameters of a process tool are updated based on the final production map.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: August 15, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ai-Jen Hung, Chen-Yen Huang, Shin-Rung Lu, Yen-Di Tsen
  • Publication number: 20170068169
    Abstract: In some embodiments, the present application is directed to a method and system for process control of a lithography tool. The method transfers a reference pattern to exposure fields of a reference workpiece to form pairs of overlapping reference layers. Misalignment between the overlapping reference layers is measured to form first and second baseline maps, and a ? baseline map is formed from the first and second baseline maps. A production pattern is transferred to exposure fields of a production workpiece to form second production layers arranged over and aligned to first production layers. Misalignment between the first and second production layers is measured to form a production map. The ? baseline map is transformed and subsequently added to the production map, to form a final production map. Parameters of a process tool are updated based on the final production map.
    Type: Application
    Filed: September 3, 2015
    Publication date: March 9, 2017
    Inventors: Ai-Jen Hung, Chen-Yen Huang, Shin-Rung Lu, Yen-Di Tsen
  • Patent number: 9588446
    Abstract: A calibration apparatus is provided. The calibration apparatus includes a wafer carrier configured to support a substrate with a patterned layer. The patterned layer includes a first exposure area and remaining exposure areas, and each of the first and the remaining exposure areas includes a first checking mark. The calibration apparatus also includes a measurement device configured to obtain a first exposure value of the first checking mark of the first exposure area by measuring the first checking mark of the first exposure area. The calibration apparatus also includes a processing module configured to calculate first calculated values of the first checking marks of the remaining exposure areas according to the first exposure value and a standard file. The illumination device is adjusted by an adjustment device of the lithography apparatus according to the first calculated values during a lithography process.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: March 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Yen Huang, Ai-Jen Hung, Shin-Rung Lu, Yen-Di Tsen
  • Publication number: 20160349633
    Abstract: A calibration apparatus is provided. The calibration apparatus includes a wafer carrier configured to support a substrate with a patterned layer. The patterned layer includes a first exposure area and remaining exposure areas, and each of the first and the remaining exposure areas includes a first checking mark. The calibration apparatus also includes a measurement device configured to obtain a first exposure value of the first checking mark of the first exposure area by measuring the first checking mark of the first exposure area. The calibration apparatus also includes a processing module configured to calculate first calculated values of the first checking marks of the remaining exposure areas according to the first exposure value and a standard file. The illumination device is adjusted by an adjustment device of the lithography apparatus according to the first calculated values during a lithography process.
    Type: Application
    Filed: May 29, 2015
    Publication date: December 1, 2016
    Inventors: Chen-Yen HUANG, Ai-Jen HUNG, Shin-Rung LU, Yen-Di TSEN
  • Patent number: 9442392
    Abstract: A method of processing first and second semiconductor wafers is provided. Each of the first and second semiconductor wafers has a first layer and a second layer over the first layer. A first lithographic process is performed on the first layer over the first semiconductor wafer using a first inter-field correction and a first intra-field correction. An overlay error of the first lithographic process is determined. A second inter-field correction and a second intra-field correction are computed based on the first inter-field correction, the first intra-field correction, and the measured overlay error. A second lithographic process is performed on the second layer over the second semiconductor wafer, based on the second inter-field correction and the second intra-field correction.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: September 13, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Di Tsen, Yi-Ping Hsieh, Chen-Yen Huang, Shin-Rung Lu, Jong-I Mou
  • Patent number: 9250619
    Abstract: A system and method of automatically calculating boundaries for a semiconductor fabrication process. The method includes selecting a first parameter for monitoring during a semiconductor fabrication process. A first set of values for the first parameter are received and a group value of the first set is determined. Each value in the first set of values is normalized. A first weighting factor is selected based on a number of values in the first set. The embodiment also includes generating a first and a second boundary value as a function of the weighting factor, the first set normalized values and the group value of the first set and applying the first and second boundary values to control the semiconductor fabrication process.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: February 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wei Hsu, Mei-Jen Wu, Yen-Di Tsen, Jo Fei Wang, Jong-I Mou, Chin-Hsiang Lin
  • Publication number: 20150348797
    Abstract: An apparatus and method for providing target thickness and surface profile uniformity control of a multi-head chemical mechanical polishing (CMP) process is disclosed. An exemplary method includes providing at least two wafers; determining a surface profile of each of the at least two wafers; determining an operation mode for a chemical mechanical polishing (CMP) process based on the surface profiles of the at least two wafers; determining a CMP polishing recipe for each of the at least two wafers based on the operation mode; and performing the CMP process on the at least two wafers based on the determined CMP polishing recipes.
    Type: Application
    Filed: August 10, 2015
    Publication date: December 3, 2015
    Inventors: Keung Hui, Jin-Ning Sung, Jong-I Mou, Soon-Kang Huang, Yen-Di Tsen
  • Patent number: 9165843
    Abstract: A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: October 20, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Long Chen, Hui-Yun Chao, Yen-Di Tsen, Jong-I Mou
  • Patent number: 9158301
    Abstract: An embodiment is a method for semiconductor processing control. The method comprises identifying a key process stage from a plurality of process stages based on a parameter of processed wafers, forecasting a trend for a wafer processed by the key process stage and some of the plurality of process stages based on the parameter, and dispatching the wafer to one of a first plurality of tools in a tuning process stage. The one of the first plurality of tools is determined based on the trend.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: October 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sunny Wu, Yen-Di Tsen, Chun-Hsien Lin, Keung Hui, Jo Fei Wang, Jong-I Mou
  • Patent number: 9123583
    Abstract: The present disclosure relates to a method of monitoring wafer topography. A position and orientation of a plurality first alignment shapes disposed on a surface of a wafer are measured. Wafer topography as a function of wafer position is modeled by subjecting the wafer to an alignment which simultaneously minimizes misalignment between the wafer and a patterning apparatus and maximizes a focus of radiation on the surface. A non-correctable error is determined as a difference between the modeled wafer topography and a measured wafer topography. A maximum non-correctable error per field is determined for a wafer, and a mean variation in the maximum non-correctable error across each field within each wafer of a lot is determined, both within a layer and across layers. These values are then verified against a set of statistical process control rules to determine if they are within a specification limit of the manufacturing process.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: September 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hsien Lin, Kuo-Hung Chao, Yi-Ping Hsieh, Yen-Di Tsen, Jui-Chun Peng, Heng-Hsin Liu, Jong-I Mou
  • Patent number: 9102033
    Abstract: An apparatus and method for providing target thickness and surface profile uniformity control of a multi-head chemical mechanical polishing (CMP) process is disclosed. An exemplary method includes providing at least two wafers; determining a surface profile of each of the at least two wafers; determining an operation mode for a chemical mechanical polishing (CMP) process based on the surface profiles of the at least two wafers; determining a CMP polishing recipe for each of the at least two wafers based on the operation mode; and performing the CMP process on the at least two wafers based on the determined CMP polishing recipes.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: August 11, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keung Hui, Jin-Ning Sung, Huang Soon Kang, Yen-Di Tsen, Jong-I Mou
  • Patent number: 9082661
    Abstract: A method includes performing a semiconductor fabrication process on a plurality of substrates. The plurality of substrates are divided into a first subset and a second subset. A rework process is performed on the second subset of the plurality of substrates but not on the first subset. A respective mean value of at least one exposure parameter for a lithography process is computed for each respective one of the first and second subsets of the plurality of substrates. A scanner overlay correction and a mean correction are applied to expose a second plurality of substrates on which the rework process has been performed. The mean correction is based on the computed mean values.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: July 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Di Tsen, Shin-Rung Lu, Jong-I Mou
  • Publication number: 20150187662
    Abstract: One or more methods or systems for performing chemical mechanical planarization (CMP) are provided. The system includes at least one of an emitter, a detector, a spectroscopic signal generator, a comparator, a spectral library, a controller or a CMP device. A spectroscopic signal is generated and is used to determine the thickness of a first material formed on or from a wafer by comparing the spectroscopic signal to a spectral library. Responsive to the thickness not being equal to the desired thickness, the controller instructs the CMP device to perform a rotation to reduce the thickness of the first material. The system and method herein increase the sensitivity of the CMP, such that the thickness of the first material is reduced with greater accuracy and precision, as compared to where the thickness is not measured between consecutive rotations of a wafer.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 2, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yen-Di Tsen, Cheng Yen-Wei, Jong-I Mou
  • Publication number: 20150170904
    Abstract: A method of processing first and second semiconductor wafers is provided. Each of the first and second semiconductor wafers has a first layer and a second layer over the first layer. A first lithographic process is performed on the first layer over the first semiconductor wafer using a first inter-field correction and a first intra-field correction. An overlay error of the first lithographic process is determined. A second inter-field correction and a second intra-field correction are computed based on the first inter-field correction, the first intra-field correction, and the measured overlay error. A second lithographic process is performed on the second layer over the second semiconductor wafer, based on the second inter-field correction and the second intra-field correction.
    Type: Application
    Filed: December 30, 2014
    Publication date: June 18, 2015
    Inventors: Yen-Di TSEN, Yi-Ping HSIEH, Chen-Yen HUANG, Shin-Rung LU, Jong-I MOU
  • Publication number: 20150125970
    Abstract: A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process.
    Type: Application
    Filed: January 16, 2015
    Publication date: May 7, 2015
    Inventors: Jui-Long CHEN, Hui-Yun CHAO, Yen-Di TSEN, Jong-I MOU
  • Patent number: 9026239
    Abstract: A method of extending advanced process control (APC) models includes constructing an APC model table including APC model parameters of a plurality of products and a plurality of work stations. The APC model table includes empty cells and cells filled with existing APC model parameters. Average APC model parameters of the existing APC model parameters are calculated, and filled into the empty cells as initial values. An iterative calculation is performed to update the empty cells with updated values.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: May 5, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Feng Tsai, Yen-Di Tsen, Jo Fei Wang, Jong-I Mou
  • Publication number: 20150027636
    Abstract: A method includes performing a semiconductor fabrication process on a plurality of substrates. The plurality of substrates are divided into a first subset and a second subset. A rework process is performed on the second subset of the plurality of substrates but not on the first subset. A respective mean value of at least one exposure parameter for a lithography process is computed for each respective one of the first and second subsets of the plurality of substrates. A scanner overlay correction and a mean correction are applied to expose a second plurality of substrates on which the rework process has been performed. The mean correction is based on the computed mean values.
    Type: Application
    Filed: October 15, 2014
    Publication date: January 29, 2015
    Inventors: Yen-Di TSEN, Shin-Rung LU, Jong-I MOU