Patents by Inventor Yen-Hsiang Fang

Yen-Hsiang Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160172253
    Abstract: A picking-up and placement process for electronic devices comprising: (a) providing a first substrate having a plurality of electronic devices formed thereon, the electronic devices being arranged in an array, and each of the electronic devices comprising a magnetic portion; (b) selectively picking-up parts of the electronic devices from the first substrate via a magnetic force generated from an electric-programmable magnetic module; and (c) bonding the parts of the electronic devices picked-up by the electric-programmable magnetic module with a second substrate.
    Type: Application
    Filed: November 30, 2015
    Publication date: June 16, 2016
    Inventors: Ming-Hsien Wu, Yen-Hsiang Fang, Chia-Hsin Chao
  • Patent number: 9356179
    Abstract: A display panel comprising a substrate, a meshed shielding pattern, a plurality of light-emitting devices and a solar cell is provided. The substrate has a first surface and a second surface opposite to the first surface, the substrate comprises a first circuit layer disposed over the first surface and a second circuit layer disposed over the second surface. The meshed shielding pattern is disposed on first surface of the substrate to define a plurality of pixel regions over the substrate. The light-emitting devices are disposed on the first surface of the substrate and electrically connected to the first circuit layer, and at least one of the light-emitting devices is disposed in one of the pixel regions. The solar cell is disposed on the second surface of the substrate and electrically connected to the second circuit layer.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: May 31, 2016
    Assignee: Industrial Technology Research Institute
    Inventors: Ming-Hsien Wu, Chia-Hsin Chao, Yen-Hsiang Fang, Yi-Chen Lin, Ying-Chien Chu, Mu-Tao Chu
  • Patent number: 9306117
    Abstract: A transfer-bonding method for light emitting devices including following steps is provided. A plurality of light emitting devices is formed over a first substrate and is arranged in array, wherein each of the light emitting devices includes a device layer and an interlayer sandwiched between the device layer and the first substrate. A protective layer is formed over the first substrate to selectively cover parts of the light emitting devices, and other parts of the light emitting devices are uncovered by the protective layer. The device layers uncovered by the protective layer are bonded with a second substrate. The interlayers uncovered by the protective layer are removed, so that parts of the device layers uncovered by the protective layer are separated from the first substrate and are transfer-bonded to the second substrate.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: April 5, 2016
    Assignee: Industrial Technology Research Institute
    Inventors: Ming-Hsien Wu, Ying-Chien Chu, Shih-Hao Wang, Yen-Hsiang Fang, Mu-Tao Chu
  • Publication number: 20160020578
    Abstract: A semiconductor laser structure is provided. The semiconductor laser comprises a central thermal shunt, a ring shaped silicon waveguide, a contiguous thermal shunt, an adhesive layer and a laser element. The central thermal shunt is located on a SOI substrate which has a buried oxide layer surrounding the central thermal shunt. The ring shaped silicon waveguide is located on the buried oxide layer and surrounds the central thermal shunt. The ring shaped silicon waveguide includes a P-N junction of a p-type material portion, an n-type material portion and a depletion region there between. The contiguous thermal shunt covers a portion of the buried oxide layer and surrounds the ring shaped silicon waveguide. The adhesive layer covers the ring shaped silicon waveguide and the buried oxide layer. The laser element covers the central thermal shunt, the adhesive layer and the contiguous thermal shunt.
    Type: Application
    Filed: September 24, 2015
    Publication date: January 21, 2016
    Inventors: Jui-Ying Lin, Yen-Hsiang Fang, Chia-Hsin Chao, Yao-Jun Tsai, Yi-Chen Lin
  • Patent number: 9171779
    Abstract: A semiconductor laser structure is provided. The semiconductor laser comprises a central thermal shunt, a ring shaped silicon waveguide, a contiguous thermal shunt, an adhesive layer and a laser element. The central thermal shunt is located on a SOI substrate which has a buried oxide layer surrounding the central thermal shunt. The ring shaped silicon waveguide is located on the buried oxide layer and surrounds the central thermal shunt. The ring shaped silicon waveguide includes a P-N junction of a p-type material portion, an n-type material portion and a depletion region there between. The contiguous thermal shunt covers a portion of the buried oxide layer and surrounds the ring shaped silicon waveguide. The adhesive layer covers the ring shaped silicon waveguide and the buried oxide layer. The laser element covers the central thermal shunt, the adhesive layer and the contiguous thermal shunt.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: October 27, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Jui-Ying Lin, Yen-Hsiang Fang, Chia-Hsin Chao, Yao-Jun Tsai, Yi-Chen Lin
  • Patent number: 9112077
    Abstract: A semiconductor structure including a silicon substrate, a nucleation layer and a plurality of multi-layer sets is provided. The nucleation layer is disposed on the silicon substrate. The multi-layer sets are stacked over the nucleation layer, and each of the multi-layer sets includes a plurality of first sub-layers and a plurality of second sub-layers stacked alternately. A material of the first sub-layers and the second sub-layers includes Al-containing III-V group compound, wherein an average content of aluminum of the multi-layer sets decreases as a minimum distance between each of the multi-layer sets and the silicon substrate increases, and an aluminum content of the first sub-layers is different from an aluminum content of the second sub-layers.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: August 18, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Chen-Zi Liao, Chih-Wei Hu, Hsun-Chih Liu, Yen-Hsiang Fang, Rong Xuan
  • Publication number: 20150179880
    Abstract: A nitride light emitting diode structure including a first type doped semiconductor layer, a second type doped semiconductor layer, a light emitting layer, a first metal pad, a second metal pad and a magnetic film is disclosed. The magnetic film disposed between the first metal pad and the first type doped semiconductor layer includes a zinc oxide (ZnO) layer doped with cobalt (Co). The content of Co in the ZnO layer ranges from 5% to 25% by molar ratio.
    Type: Application
    Filed: December 24, 2013
    Publication date: June 25, 2015
    Applicant: Industrial Technology Research Institute
    Inventors: Yen-Hsiang Fang, Rong Xuan, Chia-Lung Tsai, Yu-Hsiang Chang
  • Publication number: 20150111329
    Abstract: A transfer-bonding method for light emitting devices including following steps is provided. A plurality of light emitting devices is formed over a first substrate and is arranged in array, wherein each of the light emitting devices includes a device layer and an interlayer sandwiched between the device layer and the first substrate. A protective layer is formed over the first substrate to selectively cover parts of the light emitting devices, and other parts of the light emitting devices are uncovered by the protective layer. The device layers uncovered by the protective layer are bonded with a second substrate. The interlayers uncovered by the protective layer are removed, so that parts of the device layers uncovered by the protective layer are separated from the first substrate and are transfer-bonded to the second substrate.
    Type: Application
    Filed: December 27, 2014
    Publication date: April 23, 2015
    Inventors: Ming-Hsien Wu, Ying-Chien Chu, Shih-Hao Wang, Yen-Hsiang Fang, Mu-Tao Chu
  • Publication number: 20150108508
    Abstract: A display panel comprising a substrate, a meshed shielding pattern, a plurality of light-emitting devices and a solar cell is provided. The substrate has a first surface and a second surface opposite to the first surface, the substrate comprises a first circuit layer disposed over the first surface and a second circuit layer disposed over the second surface. The meshed shielding pattern is disposed on first surface of the substrate to define a plurality of pixel regions over the substrate. The light-emitting devices are disposed on the first surface of the substrate and electrically connected to the first circuit layer, and at least one of the light-emitting devices is disposed in one of the pixel regions. The solar cell is disposed on the second surface of the substrate and electrically connected to the second circuit layer.
    Type: Application
    Filed: December 30, 2014
    Publication date: April 23, 2015
    Inventors: Ming-Hsien Wu, Chia-Hsin Chao, Yen-Hsiang Fang, Yi-Chen Lin, Ying-Chien Chu, Mu-Tao Chu
  • Publication number: 20150063386
    Abstract: A semiconductor laser structure is provided. The semiconductor laser comprises a central thermal shunt, a ring shaped silicon waveguide, a contiguous thermal shunt, an adhesive layer and a laser element. The central thermal shunt is located on a SOI substrate which has a buried oxide layer surrounding the central thermal shunt. The ring shaped silicon waveguide is located on the buried oxide layer and surrounds the central thermal shunt. The ring shaped silicon waveguide includes a P-N junction of a p-type material portion, an n-type material portion and a depletion region there between. The contiguous thermal shunt covers a portion of the buried oxide layer and surrounds the ring shaped silicon waveguide. The adhesive layer covers the ring shaped silicon waveguide and the buried oxide layer. The laser element covers the central thermal shunt, the adhesive layer and the contiguous thermal shunt.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 5, 2015
    Inventors: Jui-Ying Lin, Yen-Hsiang Fang, Chia-Hsin Chao, Yao-Jun Tsai, Yi-Chen Lin
  • Patent number: 8946775
    Abstract: A nitride semiconductor structure is provided. The nitride semiconductor structure at least includes a silicon substrate, a AlN layer, a AlGaN layer and a GaN layer formed on the AlGaN layer. The silicon substrate has a surface tilted at 0<tilted?0.5° with respect to a axis perpendicular to a (111) crystal plane, and the AlN layer is formed on the surface. The AlGaN layer is formed on the AlN layer. Moreover, an Al content in the AlGaN layer is decreased gradually in a layer thickness direction from the silicon substrate side toward the GaN layer side.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: February 3, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Chen-Zi Liao, Chih-Wei Hu, Yen-Hsiang Fang, Rong Xuan
  • Patent number: 8779468
    Abstract: A nitride semiconductor structure including a silicon substrate, a nucleation layer, a discontinuous defect blocking layer, a buffer layer and a nitride semiconductor layer is provided. The nucleation layer disposed on the silicon substrate, wherein the nucleation layer has a defect density d1. A portion of the nucleation layer is covered by the discontinuous defect blocking layer. The buffer layer is disposed on the discontinuous defect blocking layer and a portion of the nucleation layer that is not covered by the discontinuous defect blocking layer. The nitride semiconductor layer is disposed on the buffer layer. A ratio of a defect density d2 of the nitride semiconductor layer to the defect density d1 of the nucleation layer is less than or equal to about 0.5, at a location where about 1 micrometer above the interface between the nitride semiconductor layer and the buffer layer.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: July 15, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Yen-Hsiang Fang, Chien-Pin Lu, Chen-Zi Liao, Rong Xuan, Yi-Keng Fu, Chih-Wei Hu, Hsun-Chih Liu
  • Publication number: 20140124833
    Abstract: A nitride semiconductor structure including a silicon substrate, a nucleation layer, a discontinuous defect blocking layer, a buffer layer and a nitride semiconductor layer is provided. The nucleation layer disposed on the silicon substrate, wherein the nucleation layer has a defect density d1. A portion of the nucleation layer is covered by the discontinuous defect blocking layer. The buffer layer is disposed on the discontinuous defect blocking layer and a portion of the nucleation layer that is not covered by the discontinuous defect blocking layer. The nitride semiconductor layer is disposed on the buffer layer. A ratio of a defect density d2 of the nitride semiconductor layer to the defect density d1 of the nucleation layer is less than or equal to about 0.5, at a location where about 1 micrometer above the interface between the nitride semiconductor layer and the buffer layer.
    Type: Application
    Filed: December 26, 2012
    Publication date: May 8, 2014
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yen-Hsiang Fang, Chien-Pin Lu, Chen-Zi Liao, Rong Xuan, Yi-Keng Fu, Chih-Wei Hu, Hsun-Chih Liu
  • Publication number: 20140103354
    Abstract: A nitride semiconductor structure including a silicon substrate, a nucleation layer, a buffer layer and a nitride semiconductor layer is provided. The nucleation layer disposed on the silicon substrate includes a cubic silicon carbon nitride (SiCN) layer. The buffer layer is disposed on the nucleation layer. The nitride semiconductor layer is disposed on the buffer layer.
    Type: Application
    Filed: October 9, 2013
    Publication date: April 17, 2014
    Applicant: Industrial Technology Research Institute
    Inventors: Chih-Wei Hu, Chen-Zi Liao, Yen-Hsiang Fang, Rong Xuan
  • Publication number: 20140097442
    Abstract: A nitride semiconductor device includes a silicon substrate, a nucleation layer, a first buffer layer, a first type nitride semiconductor layer, a light-emitting layer and a second type nitride semiconductor layer is provided. The nucleation layer is disposed on the silicon substrate. The first buffer layer is disposed on the nucleation layer. The first buffer layer includes a dopant and Gallium, and an atomic radius of the dopant is larger than an atomic radius of Gallium. The first type nitride semiconductor layer is disposed over the first buffer layer. The light-emitting layer is disposed on the first type nitride semiconductor layer. The second type nitride semiconductor layer is disposed on the light-emitting layer.
    Type: Application
    Filed: October 9, 2012
    Publication date: April 10, 2014
    Applicant: Industrial Technology Research Institute
    Inventors: Yen-Hsiang Fang, Chen-Zi Liao, Rong Xuan, Chien-Pin Lu, Yi-Keng Fu, Chih-Wei Hu, Hsun-Chih Liu
  • Publication number: 20140097443
    Abstract: A nitride semiconductor device includes a silicon substrate, a nucleation layer, a buffer layer, a first type nitride semiconductor stacked layer, a light-emitting layer and a second type nitride semiconductor layer. The nucleation layer is disposed on the silicon substrate. The buffer layer is disposed on the nucleation layer. The first type nitride semiconductor stacked layer is disposed on the buffer layer. The first type nitride semiconductor stacked layer being a plurality of lattice mismatch stacked layers includes a plurality of first nitride semiconductor layers and a plurality of second nitride semiconductor layers. The first nitride semiconductor layers and the second nitride semiconductor layers are stacked alternately, and the first nitride semiconductor layers and the second nitride semiconductor layers are different material. The light-emitting layer is disposed on the first type nitride semiconductor stacked layer.
    Type: Application
    Filed: October 9, 2012
    Publication date: April 10, 2014
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yen-Hsiang Fang, Rong Xuan, Chen-Zi Liao, Yi-Keng Fu, Chih-Wei Hu, Chien-Pin Lu, Hsun-Chih Liu
  • Publication number: 20140097444
    Abstract: A nitride semiconductor device includes a silicon substrate, a nucleation layer, a buffer layer, a first type nitride semiconductor layer, a light-emitting layer and a second type nitride semiconductor layer is provided. The nucleation layer is disposed on the silicon substrate. The buffer layer is disposed on the nucleation layer. The first type nitride semiconductor layer is disposed on the buffer layer. The first type nitride semiconductor layer is doped with a first type dopant, at least one of the buffer layer and the first type nitride semiconductor layer comprises a codopant distributed therein, and an atomic radius of the codopant is larger than an atomic radius of the first type dopant. The light-emitting layer is disposed on the first type nitride semiconductor layer. The second type nitride semiconductor layer is disposed on the light-emitting layer, the second type nitride semiconductor layer comprising a second type dopant.
    Type: Application
    Filed: October 9, 2012
    Publication date: April 10, 2014
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yen-Hsiang Fang, Chen-Zi Liao, Rong Xuan, Chien-Pin Lu, Yi-Keng Fu, Chih-Wei Hu, Hsun-Chih Liu
  • Patent number: 8674393
    Abstract: A substrate structure is described, including a starting substrate, crystal piers on the starting substrate, and a mask layer. The mask layer covers an upper portion of the sidewall of each crystal pier, is connected between the crystal piers at its bottom, and is separated from the starting substrate by an empty space between the crystal piers. An epitaxial substrate structure is also described, which can be formed by growing an epitaxial layer over the above substrate structure form the crystal piers. The crystal piers may be broken after the epitaxial layer is grown.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: March 18, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Yih-Der Guo, Chu-Li Chao, Yen-Hsiang Fang, Ruey-Chyn Yeh, Kun-Fong Lin
  • Publication number: 20140054593
    Abstract: A nitride semiconductor structure is provided. The nitride semiconductor structure at least includes a silicon substrate, a AlN layer, a AlGaN layer and a GaN layer formed on the AlGaN layer. The silicon substrate has a surface tilted at 0<tilted?0.5° with respect to a axis perpendicular to a (111) crystal plane, and the AlN layer is formed on the surface. The AlGaN layer is formed on the AlN layer. Moreover, an Al content in the AlGaN layer is decreased gradually in a layer thickness direction from the silicon substrate side toward the GaN layer side.
    Type: Application
    Filed: August 22, 2012
    Publication date: February 27, 2014
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chen-Zi Liao, Chih-Wei Hu, Yen-Hsiang Fang, Rong Xuan
  • Patent number: 8604487
    Abstract: A nitride semiconductor substrate and a method for manufacturing the same are provided. The nitride semiconductor substrate includes a base material, a patterned nitride semiconductor, a protection layer, and a nitride semiconductor layer. The patterned nitride semiconductor layer is located on the base material and includes a plurality of nanorod structures and a plurality of block patterns, and an upper surface of the nanorod structures is substantially coplanar with an upper surface of the block patterns. The protection layer covers a side wall of the nanorod structure sand a side wall of the block patterns. The nitride semiconductor layer is located on the patterned nitride semiconductor layer, and a plurality of nanopores are located between the nitride semiconductor layer and the patterned nitride semiconductor layer.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: December 10, 2013
    Assignee: Industrial Technology Research Institute
    Inventors: Yen-Hsiang Fang, Chu-Li Chao, Chih-Wei Hu, Yih-Der Guo