Abstract: A method includes following steps. An image of a wafer is captured. A first contact region in the captured image at which the first conductive contact is rendered is identified. A second contact region in the captured image at which the second conductive contact is rendered is identified. The second conductive contact is determined as not shorted to the first conductive contact, in response to the identified second contact region in the captured image is darker than the identified first contact region in the captured image.

Abstract: A method includes capturing an image of a wafer, the wafer comprising a first conductive contact over an active region of the wafer and a second conductive contact over a shallow trench isolation (STI) region abutting the active region; identifying a brightness of a first contact region in the captured image at which the first conductive contact is rendered; identifying a brightness of a second contact region in the captured image at which the second conductive contact is rendered; and in response to the identified brightness of the first contact region in the captured image being substantially the same as the identified brightness of the second contact region in the captured image, determining that the second conductive contact is shorted to the first conductive contact.

Abstract: A method includes capturing an image of a wafer, the wafer comprising a first conductive contact over an active region of the wafer and a second conductive contact over a shallow trench isolation (STI) region abutting the active region; identifying a brightness of a first contact region in the captured image at which the first conductive contact is rendered; identifying a brightness of a second contact region in the captured image at which the second conductive contact is rendered; and in response to the identified brightness of the first contact region in the captured image being substantially the same as the identified brightness of the second contact region in the captured image, determining that the second conductive contact is shorted to the first conductive contact.

Abstract: A method of fabricating a semiconductor structure includes forming first and second features in a scribe region of a semiconductor substrate in which the first feature has a first electrical resistance, the second feature has a second electrical resistance, and the first electrical resistance is different form the second electrical resistance; forming an interlayer dielectric layer over the first and second features; and forming a first contact in the interlayer dielectric layer and connected to the first feature and a second contact in the interlayer dielectric layer and connected to the second feature.

Abstract: A method of fabricating a semiconductor structure includes forming first and second features in a scribe region of a semiconductor substrate in which the first and second features are electrically isolated from each other; forming an interlayer dielectric layer over the first and second features; and forming a first contact in the interlayer dielectric layer and connected to the first feature and a second contact in the interlayer dielectric layer and connected to the second feature.

Abstract: A method of fabricating a semiconductor structure includes forming first and second features in a scribe region of a semiconductor substrate in which the first feature has a first electrical resistance, the second feature has a second electrical resistance, and the first electrical resistance is different form the second electrical resistance; forming an interlayer dielectric layer over the first and second features; and forming a first contact in the interlayer dielectric layer and connected to the first feature and a second contact in the interlayer dielectric layer and connected to the second feature.

Abstract: A method of fabricating a semiconductor structure includes forming first and second features in a scribe region of a semiconductor substrate in which the first and second features are electrically isolated from each other; forming an interlayer dielectric layer over the first and second features; and forming a first contact in the interlayer dielectric layer and connected to the first feature and a second contact in the interlayer dielectric layer and connected to the second feature.

Abstract: An embodiment semiconductor device includes a substrate such as a silicon or silicon-containing film, a pixel array supported by the substrate, and a metal stress release feature arranged around a periphery of the pixel array. The metal stress release feature may be formed from metal strips or discrete metal elements. The metal stress release feature may be arranged in a stress release pattern that uses a single line or a plurality of lines. The metal stress release pattern may also use metal corner elements at ends of the lines.

Abstract: An embodiment semiconductor device includes a substrate such as a silicon or silicon-containing film, a pixel array supported by the substrate, and a metal stress release feature arranged around a periphery of the pixel array. The metal stress release feature may be formed from metal strips or discrete metal elements. The metal stress release feature may be arranged in a stress release pattern that uses a single line or a plurality of lines. The metal stress release pattern may also use metal corner elements at ends of the lines.

Abstract: An embodiment semiconductor device includes a substrate such as a silicon or silicon-containing film, a pixel array supported by the substrate, and a metal stress release feature arranged around a periphery of the pixel array. The metal stress release feature may be formed from metal strips or discrete metal elements. The metal stress release feature may be arranged in a stress release pattern that uses a single line or a plurality of lines. The metal stress release pattern may also use metal corner elements at ends of the lines.

Abstract: An embodiment semiconductor device includes a substrate such as a silicon or silicon-containing film, a pixel array supported by the substrate, and a metal stress release feature arranged around a periphery of the pixel array. The metal stress release feature may be formed from metal strips or discrete metal elements. The metal stress release feature may be arranged in a stress release pattern that uses a single line or a plurality of lines. The metal stress release pattern may also use metal corner elements at ends of the lines.

Abstract: An implanting method for forming a photodiode comprises providing a substrate with a first conductivity, growing an epitaxial layer on the substrate, implanting ions with a second conductivity in the epitaxial layer from a front side of the substrate and implanting ions with the first conductivity in the epitaxial layer from the front side of the substrate to form a photo active region adjacent to the front side and a photo inactive region underneath the photo active region. By employing the implanting method, an average doping density of the photo active region is approximately ten times more than an average doping density of the photo inactive region.

Abstract: An implanting method for forming a photodiode comprises providing a substrate with a first conductivity, growing an epitaxial layer on the substrate, implanting ions with a second conductivity in the epitaxial layer from a front side of the substrate and implanting ions with the first conductivity in the epitaxial layer from the front side of the substrate to form a photo active region adjacent to the front side and a photo inactive region underneath the photo active region. By employing the implanting method, an average doping density of the photo active region is approximately ten times more than an average doping density of the photo inactive region.