Patents by Inventor Yen-Huei Chen

Yen-Huei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250124966
    Abstract: A memory device includes a memory array including a plurality of word lines, each of the plurality of word lines operatively coupled to a corresponding set of memory cells, and a controller operatively coupled to the memory array. The controller is configured to receive a first address signal indicating a first word line that is physically arranged with respect to the controller by a first distance, assert the first word line through a first signal with a first pulse width, receive a second address signal indicating a second word line that is physically arranged with respect to the controller by a second distance, assert the second word line through a second signal with a second pulse width, and adjust one of the first pulse width or the second pulse width based on the first distance and the second distance.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 17, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hidehiro Fujiwara, Yi-Hsin Nien, Venkateswara Reddy Konudula, Nikhil Puri, Yen-Huei Chen
  • Publication number: 20250118632
    Abstract: A memory device may comprise a substrate, a plurality of memory cells, and a header device. The substrate may have a first side and a second side opposite to each other. The plurality of memory cells may be formed on the first side of the substrate. The header device may be formed on the first side of the substrate. The header device can be configured to selectively couple a supply voltage through a first combination of power delivery paths or a second combination of power delivery paths to the plurality of memory cells based on a control signal.
    Type: Application
    Filed: October 10, 2023
    Publication date: April 10, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Hsin Nien, Chih-Yu Lin, Hidehiro Fujiwara, Yen-Huei Chen
  • Patent number: 12260903
    Abstract: A memory array is disclosed. The memory array includes a plurality of memory cells disposed over a substrate. Each of the memory cells is coupled to a corresponding one of a plurality of word lines and a corresponding one of a plurality of bit line pairs. First four of the memory cells that are coupled to four consecutive ones of the word lines and to a first one of the bit line pairs are abutted to one another on the substrate along a single lateral direction.
    Type: Grant
    Filed: July 12, 2022
    Date of Patent: March 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Hsin Nien, Hidehiro Fujiwara, Chih-Yu Lin, Yen-Huei Chen
  • Patent number: 12260904
    Abstract: A memory device is provided. The memory device includes a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns. A first column of the plurality of columns of the matrix includes a first plurality of memory cells of the plurality of memory cells, a first pair of bit lines connected to each of the first plurality of bit cells, and a second pair of bit lines connectable to the first pair of bit lines through a plurality of switches.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: March 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Chia-En Huang, Yen-Huei Chen, Jui-Che Tsai, Yih Wang
  • Publication number: 20250094126
    Abstract: A memory circuit includes a column of memory cells configured to receive a set of kth bits of a number H of bits of each input data element of a plurality of input data elements, and each memory cell of the column of memory cells is configured to multiply the kth bit of a corresponding input data element of the plurality of data elements with a first weight data element stored in the memory cell, and to generate a corresponding first product data element. The memory circuit includes an adder tree configured to generate a summation data element based on each of the first product data elements.
    Type: Application
    Filed: December 4, 2024
    Publication date: March 20, 2025
    Inventors: Yu-Der CHIH, Hidehiro FUJIWARA, Yi-Chun SHIH, Po-Hao LEE, Yen-Huei CHEN, Chia-Fu LEE, Jonathan Tsung-Yung CHANG
  • Publication number: 20250078889
    Abstract: Systems and method are provided for a memory circuit. In embodiments, the circuit includes a plurality of memory cells corresponding to a word of data and a global write word line. A plurality of local write lines are connected to a subset of the plurality of memory cells of the word of data. Selection logic is configured to activate a particular subset of memory cells for writing via a particular local write line based on a signal on the global write word line and a selection signal associated with the particular subset of memory cells.
    Type: Application
    Filed: November 15, 2024
    Publication date: March 6, 2025
    Inventors: Yi-Hsin Nien, Hidehiro Fujiwara, Yen-Huei Chen
  • Publication number: 20250078878
    Abstract: A memory device in an integrated circuit is provided, including an input/output (I/O) circuit, a first memory segment and a second memory segment that separated from the first memory segment in a first direction, a first pair of data lines on a first side of the integrated circuit, extending in the first direction and configured to couple the first memory segment to the I/O circuit, and a second pair of data lines separated from the first pair of data lines in a second direction, different from the first direction, on a second side, opposite to the first side, of the integrated circuit, and configured to couple the second memory segment to the I/O circuit. A first width of the first pair of data lines is different from a second width of the second pair of data lines.
    Type: Application
    Filed: November 19, 2024
    Publication date: March 6, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Sheng WANG, Kao-Cheng LIN, Yangsyu LIN, Yen-Huei CHEN, Cheng Hung LEE, Jonathan Tsung-Yung CHANG
  • Patent number: 12245412
    Abstract: A device includes first and second gate electrodes, a word line and a first metal island. The first gate electrode corresponds to transistors of a memory cell. The second gate electrode is separated from the first gate electrode and corresponds to the transistors. The word line is coupled to the memory cell and located between the first and the second gate electrodes. The first metal island is configured to couple a first power supply to the memory cell. A first boundary of the first metal island is located between first and second boundaries of the first gate electrode and is located between first and second boundaries of the word line, and each of the first boundary of the first gate electrode and the first boundary of the word line is located between first and second boundaries of the first metal island.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hidehiro Fujiwara, Wei-Min Chan, Chih-Yu Lin, Yen-Huei Chen, Hung-Jen Liao
  • Publication number: 20250063709
    Abstract: A method (of manufacturing a memory device) includes forming active regions extending in a first direction; over the active regions, doing as follows including, forming gate structures extending in a second direction perpendicular to the first direction, and forming contact-to-source/drain structures (MD structures) which extend in the second direction and are interspersed among corresponding ones of the gate structures; forming via-to-gate/MD (VGD) structures over corresponding ones of the gate structures and the MD structures; in a first metallization layer over the VGD structures, forming first front-side segments extending in the first direction and including one or more front-side routing (FRTE) segments; under the active regions, forming buried segment-to-source/drain structures (BVD structures); and in a first buried metallization layer under the BVD structures, forming first back-side segments extending in the first direction and including one or more first back-side power grid (BPG) segments.
    Type: Application
    Filed: November 5, 2024
    Publication date: February 20, 2025
    Inventors: Hidehiro FUJIWARA, Chih-Yu LIN, Yen-Huei CHEN, Wei-Chang ZHAO, Yi-Hsin NIEN
  • Patent number: 12230318
    Abstract: A memory device includes a first word line and a second word line. A first portion of the first word line is formed in a first metal layer, a second portion of the first word line is formed in a second metal layer above the first metal layer, and a third portion of the first word line is formed in a third metal layer below the second metal layer. A first portion of the second word line is formed in the first metal layer. A second portion of the second word line is formed in the second metal layer. The first portion, the second portion, and the third portion of the first word line have sizes that are different from each other, and the first portion and the second portion of the second word line have sizes that are different from each other.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsin Nien, Wei-Chang Zhao, Chih-Yu Lin, Hidehiro Fujiwara, Yen-Huei Chen, Ru-Yu Wang
  • Publication number: 20250054537
    Abstract: A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.
    Type: Application
    Filed: July 30, 2024
    Publication date: February 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hidehiro Fujiwara, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Wei-Chang Zhao
  • Publication number: 20250046367
    Abstract: A memory circuit includes an array including a plurality of memory cells arranged across a plurality of columns and a plurality of voltage control circuits, each of the plurality of voltage control circuits operatively coupled to the memory cells of a corresponding one of the plurality of columns. Each of the plurality of voltage control circuits includes a first portion configured to provide a first voltage drop in coupling a supply voltage to the memory cells of the corresponding column and a second portion configured to provide a second voltage drop in coupling the supply voltage to the memory cells of the corresponding column. The first voltage drop is substantially smaller than the second voltage drop.
    Type: Application
    Filed: February 20, 2024
    Publication date: February 6, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kao-Cheng Lin, Yen-Huei Chen, Wei Min Chan, Hidehiro Fujiwara, Wei-Cheng Wu, Pei-Yuan Li, Chien-Chen Lin, Shang Lin Wu
  • Publication number: 20250014614
    Abstract: A memory device includes a first memory array comprising first memory cells; a second memory array comprising second memory cells; a third memory array comprising third memory cells, the second memory array interposed between the first memory array and the third memory array along a lateral direction; a first bit line segment extending along the lateral direction and coupled to each of the first memory cells; a second bit line segment extending along the lateral direction and coupled to each of the second memory cells; and a third bit line segment extending along the lateral direction and coupled to each of the third memory cells. The first bit line segment is formed in a first metallization layer, the second bit line segment is formed in a second metallization layer, and the third bit line segment is formed in a third metallization layer.
    Type: Application
    Filed: October 20, 2023
    Publication date: January 9, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Hsin Nien, Hidehiro Fujiwara, Chih-Yu Lin, Yen-Huei Chen
  • Publication number: 20250006815
    Abstract: A method includes forming a first bottom-tier transistor; forming a second bottom-tier transistor, the first and second bottom-tier transistors sharing a same source/drain region; forming a first top-tier transistor over the first bottom-tier transistor, the first top-tier transistor comprising a first channel layer and a first gate structure around the first channel layer; forming a second top-tier transistor over the second bottom-tier transistor, the second top-tier transistor comprising a second channel layer and a second gate structure around the second channel layer, the first and second top-tier transistors sharing a same source/drain region, wherein from a top view, a first dimension of the first channel layer in a lengthwise direction of the first gate structure is different than a second dimension of the second channel layer in the lengthwise direction of the first gate structure.
    Type: Application
    Filed: June 27, 2023
    Publication date: January 2, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kao-Cheng LIN, Cheng-Yin WANG, Yen Lin CHUNG, Wei Min CHAN, Yen-Huei CHEN
  • Patent number: 12183417
    Abstract: A memory device in an integrated circuit is provided, including an input/output (I/O) circuit, a first memory segment and a second memory segment that separated from the first memory segment in a first direction, a first pair of data lines on a first side of the integrated circuit, extending in the first direction and configured to couple the first memory segment to the I/O circuit, and a second pair of data lines separated from the first pair of data lines in a second direction, different from the first direction, on a second side, opposite to the first side, of the integrated circuit, and configured to couple the second memory segment to the I/O circuit. A first width of the first pair of data lines is different from a second width of the second pair of data lines.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: December 31, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Sheng Wang, Kao-Cheng Lin, Yangsyu Lin, Yen-Huei Chen, Cheng Hung Lee, Jonathan Tsung-Yung Chang
  • Patent number: 12176026
    Abstract: A static random access memory includes a first and second memory cell array, a first word line, a bit line, a bit line bar, a primary driver circuit, and a first and second supplementary driver circuit. The first supplementary driver circuit is configured to pull a voltage of a first signal of the bit line or a second signal of the bit line bar to a first voltage level during a write operation in response to a supplementary driver circuit enable signal. The second supplementary driver circuit is configured to sense the voltage of the first or second signal. The second supplementary driver circuit includes a first pass-gate transistor. A first terminal of the first pass-gate transistor is coupled to a reference voltage supply. A second terminal of the first pass-gate transistor is electrically floating. A third terminal of the first pass-gate transistor is coupled to a first node.
    Type: Grant
    Filed: June 12, 2023
    Date of Patent: December 24, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Yu Lin, Wei-Cheng Wu, Kao-Cheng Lin, Yen-Huei Chen
  • Patent number: 12164882
    Abstract: A memory circuit includes a selection circuit, a column of memory cells, and an adder tree. The selection circuit is configured to receive input data elements, each input data element including a number of bits equal to H, and output a selected set of kth bits of the H bits of the input data elements. Each memory cell of the column of memory cells includes a first storage unit configured to store a first weight data element and a first multiplier configured to generate a first product data element based on the first weight data element and a first kth bit of the selected set of kth bits. The adder tree is configured to generate a summation data element based on each of the first product data elements.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Der Chih, Hidehiro Fujiwara, Yi-Chun Shih, Po-Hao Lee, Yen-Huei Chen, Chia-Fu Lee, Jonathan Tsung-Yung Chang
  • Publication number: 20240404566
    Abstract: Header circuitry for a memory device includes multiple backside power rails that form distinct voltage sources for a plurality of switching devices in the header circuitry. The header circuitry includes at least one region of a first conductivity type. A first section in the first region includes one backside power rail (BPR) that forms a first voltage source that provides a first voltage. A second section in the same first region includes another BPR that forms a second voltage source that provides a second voltage that is different from the first voltage.
    Type: Application
    Filed: July 25, 2024
    Publication date: December 5, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Haruki MORI, Chien-Chi TIEN, Chia-En HUANG, Hidehiro FUJIWARA, Yen-Huei CHEN, Feng-Lun CHEN
  • Publication number: 20240404588
    Abstract: A semiconductor device includes a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell operatively arranged along a first one of a plurality of columns, and operatively arranged in a first one, a second one, a third one, and a fourth one of a plurality of rows, respectively. The first column operatively corresponds to a first pair of bit lines and a second pair of bit lines. The first to fourth rows operatively correspond to a first word line, a second word line, a third word line, and a fourth word line, respectively. The first pair of bit lines are operatively coupled to the first and second memory cells. The second pair of bit lines are operatively coupled to the third and fourth memory cells.
    Type: Application
    Filed: June 2, 2023
    Publication date: December 5, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Hsin Nien, Chih-Yu Lin, Hidehiro Fujiwara, Yen-Huei Chen
  • Patent number: 12159688
    Abstract: Systems and method are provided for a memory circuit. In embodiments, the circuit includes a plurality of memory cells corresponding to a word of data and a global write word line. A plurality of local write lines are connected to a subset of the plurality of memory cells of the word of data. Selection logic is configured to activate a particular subset of memory cells for writing via a particular local write line based on a signal on the global write word line and a selection signal associated with the particular subset of memory cells.
    Type: Grant
    Filed: June 5, 2023
    Date of Patent: December 3, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yi-Hsin Nien, Hidehiro Fujiwara, Yen-Huei Chen