Patents by Inventor Yen-Huei Chen

Yen-Huei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10431295
    Abstract: A static random access memory (SRAM) that includes a memory cell comprising at least two p-type pass gates. The SRAM also includes a first data line connected to the memory cell, a second data line connected to the memory cell and a voltage control unit connected to the first data line, wherein the voltage control unit is configured to control the memory cell.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: October 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Wen Wang, Chih-Yu Lin, Yen-Huei Chen, Hung-Jen Liao
  • Publication number: 20190295632
    Abstract: A semiconductor memory device includes an array of memory cells arranged in a plurality of rows and columns, with each memory cell including a plurality of bit cell transistors. The semiconductor memory device further includes a plurality of write assist circuits, including one or more write assist circuits within each column of the array of memory cells, each write assist circuit configured to provide a core voltage to memory cells within the same column and to reduce the core voltage during a write operation. The array of memory cells and the plurality of write assist circuits have a common semiconductor layout.
    Type: Application
    Filed: June 10, 2019
    Publication date: September 26, 2019
    Inventors: Sahil Preet Singh, Yen-Huei Chen, Hung-Jen Liao
  • Patent number: 10411019
    Abstract: A device is disclosed that includes a memory bit cell, a first word line, a pair of metal islands and a pair of connection metal lines. The first word line is disposed in a first metal layer and is electrically coupled to the memory bit cell. The pair of metal islands are disposed in the first metal layer at opposite sides of the word line and are electrically coupled to a power supply. The pair of connection metal lines are disposed in a second metal layer and are configured to electrically couple the metal islands to the memory bit cell respectively.
    Type: Grant
    Filed: June 18, 2016
    Date of Patent: September 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hidehiro Fujiwara, Wei-Min Chan, Chih-Yu Lin, Yen-Huei Chen, Hung-Jen Liao
  • Publication number: 20190259432
    Abstract: A memory macro includes a first memory cell array, first tracking circuit, first pre-charge circuit coupled to a first end of the first tracking bit line and a second pre-charge circuit coupled to a second end of the first tracking bit line. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first set of control signals, a second set of memory cells configured as a first set of pull-down cells responsive to a second set of control signals, and a first tracking bit line. The first set of pull-down cells and first set of loading cells are configured to track a memory cell of the first memory cell array. The first and second pre-charge circuit are configured to charge the first tracking bit line to a voltage level responsive to a third set of control signals.
    Type: Application
    Filed: May 6, 2019
    Publication date: August 22, 2019
    Inventors: Chien-Kuo SU, Cheng Hung LEE, Chiting CHENG, Hung-Jen LIAO, Jonathan Tsung-Yung CHANG, Yen-Huei CHEN, Pankaj AGGARWAL, Jhon Jhy LIAW
  • Patent number: 10373964
    Abstract: A method, of writing to a memory cell, includes: causing a pulling device of the memory cell to pull a voltage level at a first data node of the memory cell toward a first supply voltage level responsive to a voltage level at a second data node of the memory cell; causing a pass gate of the memory cell to pull the voltage level at the first data node of the memory cell toward a second supply voltage level responsive to a word line signal, the second supply voltage level being different from the first supply voltage level; and limiting a driving capability of the pulling device by a resistive device, the resistive device being electrically coupled between the pulling device and a supply voltage source configured to provide a first supply voltage, the first supply voltage having the first supply voltage level.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: August 6, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Huei Chen, Hung-Jen Liao, Chih-Yu Lin, Jonathan Tsung-Yung Chang, Wei-Cheng Wu
  • Publication number: 20190237134
    Abstract: Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail.
    Type: Application
    Filed: April 5, 2019
    Publication date: August 1, 2019
    Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Yen-Huei Chen, Mahmut Sinangil
  • Publication number: 20190236241
    Abstract: A system includes a net-identifying module and a false path-eliminating module. The net-identifying module is configured to receive first and second electronic lists associated with a circuit unit, to identify a net of the circuit unit based on the first electronic list, and to provide a net information output that includes information associated with the net. The false path-eliminating module is coupled to the net-identifying module and is configured to select, in the second electronic list, a path of the circuit unit that does not traverse through the net and provide a path information output that includes information associated with the path.
    Type: Application
    Filed: April 15, 2019
    Publication date: August 1, 2019
    Inventors: Chun-Jiun Dai, Hung-Jen Liao, Wei-Min Chan, Yen-Huei Chen
  • Patent number: 10354952
    Abstract: A memory cell comprises a first word line in a first layer on a first level. The memory cell also comprises a second word line having a first portion in the first layer and a second portion in a second layer. The second layer is on a second level different from the first level. The memory cell further comprises a first via layer coupling the first portion of the second word line with the second portion of the second word line.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: July 16, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Li-Wen Wang, Yen-Huei Chen, Hung-Jen Liao
  • Patent number: 10319421
    Abstract: A memory macro includes a first set of memory cells, a second set of memory cells and a set of conductive lines. The first set of memory cells is arranged in columns and rows. Each memory cell of the first set of memory cells includes a voltage supply node configured to receive a first voltage of a first supply voltage or a second voltage of a second supply voltage. The second set of memory cells includes a set of retention circuits configured to supply the second voltage of the second supply voltage to the first set of memory cells during a sleep operational mode. The set of conductive lines is coupled to the set of retention circuits and the voltage supply node of each memory cell of the first set of memory cells.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: June 11, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Kuo Su, Cheng Hung Lee, Chiting Cheng, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Pankaj Aggarwal, Jhon Jhy Liaw
  • Patent number: 10319435
    Abstract: A semiconductor memory device includes an array of memory cells arranged in a plurality of rows and columns, with each memory cell including a plurality of bit cell transistors. The semiconductor memory device further includes a plurality of write assist circuits, including one or more write assist circuits within each column of the array of memory cells, each write assist circuit configured to provide a core voltage to memory cells within the same column and to reduce the core voltage during a write operation. The array of memory cells and the plurality of write assist circuits have a common semiconductor layout.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: June 11, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sahil Preet Singh, Yen-Huei Chen, Hung-Jen Liao
  • Publication number: 20190172501
    Abstract: A device includes a memory array. The memory array includes a first sub-bank, a second sub-bank, a strap cell and a continuous data line. The strap cell is arranged between the first sub-bank and the second sub-bank. The continuous data line includes a first portion coupled to the first sub-bank and a second portion disposed across the second sub-bank. The first portion of the continuous data line and the second portion of the continuous data line are disposed at separate layers above the strap cell.
    Type: Application
    Filed: February 1, 2019
    Publication date: June 6, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jonathan Tsung-Yung CHANG, Cheng-Hung LEE, Chi-Ting CHENG, Hung-Jen LIAO, Jhon-Jhy LIAW, Yen-Huei CHEN
  • Publication number: 20190139600
    Abstract: A static random access memory (SRAM) includes a bit cell that includes a p-type pass gate, a bit information path connected to the bit cell by the p-type pass gate, and a write multiplexer connected to the bit information path. The write multiplexer includes a p-type transistor configured to selectively couple the bit information path to a flip-flop.
    Type: Application
    Filed: January 7, 2019
    Publication date: May 9, 2019
    Inventors: Wei-Cheng WU, Wei Min CHAN, Yen-Huei CHEN, Hung-Jen LIAO, Ping-Wei WANG
  • Patent number: 10276579
    Abstract: Arrays of static random access memory (SRAM) cells and methods of fabricating the same are provided. A first communication path is disposed a first distance from an edge of the array and is operable to control access to SRAM cells of a first row of the array for write operations. A second communication path is disposed a second distance from the edge of the array and is operable to control access to SRAM cells of a second row of the array for write operations. The second distance is different than the first distance. A first conductive structure is disposed a third distance from the edge of the array and is operable to control access to the SRAM cells of the first row for read operations. A second conductive structure is disposed the third distance from the edge of the array and is operable to control access to the SRAM cells of the second row for read operations.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Yen-Huei Chen
  • Patent number: 10275561
    Abstract: A system includes a net-identifying module and a false path-eliminating module. The net-identifying module is configured to receive first and second electronic lists associated with a circuit unit, to identify a net of the circuit unit based on the first electronic list, and to provide a net information output that includes information associated with the net. The false path-eliminating module is coupled to the net-identifying module and is configured to eliminate a false path of the circuit unit in the second electronic list based on the net information output.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chun-Jiun Dai, Hung-Jen Liao, Wei-Min Chan, Yen-Huei Chen
  • Patent number: 10276231
    Abstract: Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Yen-Huei Chen, Mahmut Sinangil
  • Publication number: 20190122960
    Abstract: An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.
    Type: Application
    Filed: December 18, 2018
    Publication date: April 25, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Yu Lin, Kao-Cheng Lin, Li-Wen Wang, Yen-Huei Chen
  • Patent number: 10268787
    Abstract: A hybrid timing analysis method includes: receiving a pre-layout netlist, a post-layout netlist and a configuration file associated with an integrated circuit design; generating a first measurement script and an input stimulus waveform file according to the configuration file; performing a first dynamic timing analysis upon the pre-layout netlist by using the first measurement script and the input stimulus waveform file to generate a pre-layout simulation result; identifying at least one data path and at least one clock path according to the pre-layout simulation result; generating a second measurement script according to the at least on data path and at least one clock path; and performing a second dynamic timing analysis upon the post-layout netlist by using the second measurement script and the input stimulus waveform file to generate a first post-layout simulation result. Associated system and non-transitory computer readable medium are also provided.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Jiun Dai, Wei Min Chan, Yen-Huei Chen, Hung-Jen Liao, Jonathan Tsung-Yung Chang
  • Publication number: 20190108874
    Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 11, 2019
    Inventors: Mahmut Sinangil, Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Sahil Preet Singh
  • Publication number: 20190108875
    Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 11, 2019
    Inventors: Sahil Preet Singh, Jung-Hsuan Chen, Yen-Huei Chen, Avinash Chander, Albert Ying
  • Publication number: 20190103158
    Abstract: A circuit includes a column of memory cells, a first read data line coupled exclusively with a first subset of memory cells of the column of memory cells, a second read data line coupled exclusively with a second subset of memory cells of the column of memory cells, and a plurality of read word lines. Each read word line of the plurality of read word lines is coupled with a memory cell of the first subset of memory cells and with a memory cell of the second subset of memory cells.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 4, 2019
    Inventors: Hidehiro FUJIWARA, Li-Wen WANG, Yen-Huei CHEN, Hung-Jen LIAO