Patents by Inventor Yen-Huei Chen

Yen-Huei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180102163
    Abstract: A memory device includes a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state, and a physically unclonable function (PUF) generator. The PUF generator further includes a first sense amplifier, coupled to the plurality of memory cells, wherein while the plurality of memory cells are being accessed, the first sense amplifier is configured to compare accessing speeds of first and second memory cells of the plurality of memory cells, and based on the comparison, provide a first output signal for generating a first PUF signature.
    Type: Application
    Filed: October 7, 2016
    Publication date: April 12, 2018
    Inventors: Chien-Chen LIN, Wei-Min Chan, Chih-Yu Lin, Shih-Lien Linus Lu, Yen-Huei Chen
  • Publication number: 20180096710
    Abstract: A device includes a memory array including a first sub-bank, a second sub-bank, a first strap cell and a data line. The first strap cell is arranged between the first sub-bank and the second sub-bank. The data line includes a first portion and a second portion. The first portion is arranged across the first sub-bank. The second portion is arranged across the second sub-bank, and is coupled to the first portion via the first strap cell.
    Type: Application
    Filed: December 4, 2017
    Publication date: April 5, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jonathan Tsung-Yung Chang, Cheng-Hung Lee, Chi-Ting Cheng, Hung-Jen Liao, Jhon-Jhy Liaw, Yen-Huei Chen
  • Publication number: 20180090183
    Abstract: In accordance with some embodiments of the present disclosure, a circuit structure is provided. The circuit structure comprises a first transistor, a second transistor, a storage node and a word-line. Each of the two transistors comprises a gate, a source and a drain. The storage node is connected to the gate of the first transistor. The word-line is connected to the gate of the second transistor. The first and second transistors are serially connected. The first and second threshold voltages are respectively associated with the first and second transistors, and the first threshold voltage is lower than the second threshold voltage.
    Type: Application
    Filed: December 4, 2017
    Publication date: March 29, 2018
    Inventors: Hidehiro Fujiwara, Chih-Yu Lin, Wei-Cheng Wu, Yen-Huei Chen, Hung-Jen Liao
  • Patent number: 9928899
    Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: March 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sahil Preet Singh, Jung-Hsuan Chen, Yen-Huei Chen, Avinash Chander, Albert Ying
  • Patent number: 9922700
    Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: March 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mahmut Sinangil, Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Sahil Preet Singh
  • Patent number: 9905292
    Abstract: A three dimensional dual-port bit cell generally comprises a first portion disposed on a first tier, wherein the first portion includes a plurality of port elements. The dual-port bit cell also includes a second portion disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a latch.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: February 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei Min Chan, Wei-Cheng Wu, Yen-Huei Chen
  • Publication number: 20180053537
    Abstract: A memory macro includes a first set of memory cells, a second set of memory cells, a third set of memory cells, a set of retention circuits and a set of conductive lines. The second set of memory cells arranged in a first row arranged in a second direction. The third set of memory cells arranged in a first column arranged in a first direction. The set of retention circuits is configured to supply a second voltage value of a second supply voltage to the first set of memory cells during a sleep operational mode. The set of retention circuits is responsive to a set of control signals, and arranged in a second column arranged in the first direction. The set of conductive lines extend in the second direction, and coupled to the set of retention circuits and the voltage supply node of the first set of memory cells.
    Type: Application
    Filed: October 31, 2017
    Publication date: February 22, 2018
    Inventors: Chien-Kuo SU, Cheng Hung LEE, Chiting CHENG, Hung-Jen LIAO, Jonathan Tsung-Yung CHANG, Yen-Huei CHEN, Pankaj AGGARWAL, Jhon Jhy LIAW
  • Patent number: 9886996
    Abstract: In some embodiments, the present disclosure relates to a static random access memory (SRAM) device. The SRAM device includes a plurality of SRAM cells arranged in a plurality of rows and a plurality of columns, wherein respective SRAM cells include respective pairs of complementary data storage nodes to store respective data states. A first pair of access transistors is coupled to the complementary data storage nodes of an SRAM cell and is configured to selectively couple the complementary data storage nodes to a first pair of complementary bitlines, respectively. A second pair of access transistors is coupled to the complementary data storage nodes of the SRAM cell and is configured to selectively couple the complementary data storage nodes to a second pair of complementary bitlines, respectively.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: February 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Yen-Huei Chen, Mahmut Sinangil
  • Patent number: 9871046
    Abstract: A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fang Chen, Jhon Jhy Liaw, Min-Chang Liang, Ren-Fen Tsui, Shih-Chi Fu, Yen-Huei Chen
  • Patent number: 9865542
    Abstract: In some embodiments, an interconnect structure includes first and second metal lines, and an end-to-end portion. The first metal line is formed in a first interconnect layer, extends in length substantially along a first direction and ends at a first end portion. The second metal line is formed in the first interconnect layer, starts from a second end portion, extends in length substantially along the first direction and is misaligned with the first metal line in the first direction. The end-to-end portion couples the first metal line to the second metal line, is formed in a second interconnect layer different from the first interconnect layer, and is overlapped with the first and second end portions. A width of the end-to-end portion at where the end-to-end portion is overlapped with the first end portion is wider than a width of the first end portion by at least about 10%.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: January 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD
    Inventors: Jhon Jhy Liaw, Yen-Huei Chen
  • Patent number: 9865605
    Abstract: A memory circuit includes a first column of memory cells arranged along a first direction, a first supply voltage line extending along the first direction in a first conductive layer of the memory circuit, a second supply voltage line, a first resistive device electrically connecting the first supply voltage line and the second supply voltage line, and a supply voltage source. Each memory cell of the first column of memory cells includes a supply voltage line segment. The first supply voltage line is made of at least the supply voltage line segments of the first column of memory cells. The supply voltage source is electrically coupled with first supply voltage line through one or more conductive paths, and the second supply voltage line and the first resistive device is in a lowest resistance path of the one or more conductive paths.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: January 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Huei Chen, Hung-Jen Liao, Chih-Yu Lin, Jonathan Tsung-Yung Chang, Wei-Cheng Wu
  • Patent number: 9853035
    Abstract: A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: December 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsien-Yu Pan, Jung-Hsuan Chen, Shao-Yu Chou, Yen-Huei Chen, Hung-Jen Liao
  • Patent number: 9842627
    Abstract: A device includes a first strap cell, a first data line, and a second data line. The first strap cell is arranged between a first row of memory cells and a second row of memory cells in a memory array. A first portion of the first data line is configured to transmit data to or from a first memory cell in the first row of memory cells. The second data line and a second portion of the first data line are configured to transmit data to or from a second memory cell in the second row of memory cells.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: December 12, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jonathan Tsung-Yung Chang, Cheng-Hung Lee, Chi-Ting Cheng, Hung-Jen Liao, Jhon-Jhy Liaw, Yen-Huei Chen
  • Patent number: 9837130
    Abstract: In accordance with some embodiments of the present disclosure, a circuit structure is provided. The circuit structure comprises a first transistor, a second transistor, a storage node and a word-line. Each of the two transistors comprises a gate, a source and a drain. The storage node is connected to the gate of the first transistor. The word-line is connected to the gate of the second transistor. The first and second transistors are serially connected. The first and second threshold voltages are respectively associated with the first and second transistors, and the first threshold voltage is lower than the second threshold voltage.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: December 5, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hidehiro Fujiwara, Chih-Yu Lin, Wei-Cheng Wu, Yen-Huei Chen, Hung-Jen Liao
  • Publication number: 20170344696
    Abstract: A system includes a net-identifying module and a false path-eliminating module. The net-identifying module is configured to receive first and second electronic lists associated with a circuit unit, to identify a net of the circuit unit based on the first electronic list, and to provide a net information output that includes information associated with the net. The false path-eliminating module is coupled to the net-identifying module and is configured to eliminate a false path of the circuit unit in the second electronic list based on the net information output.
    Type: Application
    Filed: December 2, 2016
    Publication date: November 30, 2017
    Inventors: Chun-Jiun Dai, Hung-Jen Liao, Wei-Min Chan, Yen-Huei Chen
  • Publication number: 20170345485
    Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.
    Type: Application
    Filed: May 24, 2016
    Publication date: November 30, 2017
    Inventors: Mahmut Sinangil, Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Sahil Preet Singh
  • Patent number: 9824729
    Abstract: A memory macro includes a first memory cell array, a first tracking circuit and a first pre-charge circuit. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first set of control signals, a second set of memory cells configured as a first set of pull-down cells responsive to a second set of control signals, and a first tracking bit line coupled to the first set of memory cells and the second set of memory cells. The first set of pull-down cells and the first set of loading cells are configured to track a memory cell of the first memory cell array. The first pre-charge circuit is coupled to the first tracking bit line, and is configured to charge the first tracking bit line to a pre-charge voltage level responsive to a third set of control signals.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: November 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Kuo Su, Cheng Hung Lee, Chiting Cheng, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Pankaj Aggarwal, Jhon Jhy Liaw
  • Patent number: 9812191
    Abstract: A memory device includes: a memory array comprising a first plurality of bit cells arranged along a first column; and a negative bit line (NBL) circuit, coupled to the memory array. The NBL circuit includes: a first pair of conducting gates that are coupled to the first plurality of bit cells through a bit line (BL) and a bit bar line (BBL) of the first column, respectively; and a pair of trigger circuits, coupled to the first pair of conducting gates, respectively, and configured to monitor voltage levels present on the BL and BBL of the first column through the respective first pair of conducting gates, and based on the monitored voltage levels, to assert an NBL enable signal so as to cause a negative voltage to be applied on either the BL or the BBL of the first column.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: November 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Avinash Chander, Yen-Huei Chen
  • Patent number: 9799394
    Abstract: A static random access memory (SRAM) including at least a memory cell array, a first data line, a second data line, a third data line and a driver circuit. The first data line is electrically coupled with the memory cell array. The second data line is electrically coupled with the memory cell array. The driver circuit is electrically coupled with the first data line, the second data line and the third data line. The driver circuit includes a recovery circuit electrically coupled with the first data line, the second data line and the third data line. During a write operation of the SRAM, the recovery circuit is configured to pull a voltage level of the first data line to a first voltage level when the recovery circuit is enabled.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: October 24, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Cheng Wu, Kao-Cheng Lin, Wei Min Chan, Yen-Huei Chen
  • Publication number: 20170294224
    Abstract: A static random access memory (SRAM) includes a bit cell that receives an operating voltage and a reference voltage, and includes a p-type pass gate. A bit information path is connected to the bit cell by the p-type pass gate, and a pre-discharge circuit is connected to the bit information path. The pre-discharge circuit includes an n-type transistor that discharges the bit information path to the reference voltage.
    Type: Application
    Filed: June 26, 2017
    Publication date: October 12, 2017
    Inventors: Wei-Cheng WU, Wei Min CHAN, Yen-Huei CHEN, Hung-Jen LIAO, Ping-Wei WANG