Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The package comprises a die, through interlayer vias (TIVs), a dielectric film, a backside film and solder paste portions. The TIVs are disposed beside the semiconductor die and a molding compound laterally surrounds the die and the TIVs. The dielectric film is disposed on a backside of the semiconductor die, and the backside film is disposed on the dielectric film. The backside film has at least one of a coefficient of thermal expansion (CTE) and a Young's modulus larger than that of the dielectric film. The solder paste portions are disposed on the TIVs and located within openings penetrating through the dielectric film and the backside film. There is a recess located at an interface between the dielectric film and the backside film within the opening.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Abstract: A method includes forming a first redistribution structure by depositing a first dielectric layer and forming first and second conductive features on the first dielectric layer, the second conductive feature being provided with a gap exposing the first dielectric layer. The method further includes depositing a second dielectric layer on the first and second conductive features; forming first and second openings in the second dielectric layer, the first opening exposing the first conductive feature and the second opening exposing the second conductive feature and the gap; forming a first via on the first conductive feature and partially in the first opening; forming a second via on the second conductive feature and partially in the second opening and the gap; attaching a die to the first redistribution structure adjacent the first via and the second via; and encapsulating the die, the first via, and the second via with an encapsulant.

Abstract: A method includes providing a semiconductor substrate having a front side surface and a back side surface opposite to the front side surface. A photosensitive region of the semiconductor substrate is etched to form a recess. A semiconductor material is deposited on the semiconductor substrate to form a radiation sensing member filling the recess. The semiconductor material has an optical band gap energy smaller than 1.77 eV. A device layer is formed over the front side surface of the semiconductor substrate and the radiation sensing member. A trench isolation is formed in an isolation region of the semiconductor substrate and extending from the back side surface of the semiconductor substrate.

Abstract: In an embodiment, a structure includes: a first integrated circuit die including first die connectors; a first dielectric layer on the first die connectors; first conductive vias extending through the first dielectric layer, the first conductive vias connected to a first subset of the first die connectors; a second integrated circuit die bonded to a second subset of the first die connectors with first reflowable connectors; a first encapsulant surrounding the second integrated circuit die and the first conductive vias, the first encapsulant and the first integrated circuit die being laterally coterminous; second conductive vias adjacent the first integrated circuit die; a second encapsulant surrounding the second conductive vias, the first encapsulant, and the first integrated circuit die; and a first redistribution structure including first redistribution lines, the first redistribution lines connected to the first conductive vias and the second conductive vias.

Abstract: A semiconductor structure includes an ILD disposed over a semiconductive substrate, an isolation disposed between the semiconductive substrate and the ILD, and a conductive pad disposed within the semiconductive substrate, the isolation and the ILD. A top surface of the conductive pad is substantially parallel with two surfaces of the semiconductive substrate. The top surface of the conductive pad is between the two surfaces of the semiconductive substrate. Sidewalls of the conductive pad are in direct contact with the ILD and the isolation.

Abstract: A semiconductor structure includes a transceiver, a molding surrounding the transceiver, and a RDL disposed over the transceiver. The RDL includes an antenna and a dielectric layer. The antenna is disposed over and electrically connected to the transceiver. The dielectric layer surrounds the antenna. The antenna includes an elongated portion and a via portion. The elongated portion extends over the molding, and the via portion is electrically connected to the transceiver.

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The package comprises a die, through interlayer vias (TIVs), a dielectric film, a backside film and solder paste portions. The TIVs are disposed beside the semiconductor die and a molding compound laterally surrounds the die and the TIVs. The dielectric film is disposed on a backside of the semiconductor die, and the backside film is disposed on the dielectric film. The backside film has at least one of a coefficient of thermal expansion (CTE) and a Young's modulus larger than that of the dielectric film. The solder paste portions are disposed on the TIVs and located within openings penetrating through the dielectric film and the backside film. There is a recess located at an interface between the dielectric film and the backside film within the opening.

Abstract: A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 ?m. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 ?m. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 ?m. In another embodiment the underbump metallization has a first dimension that is less than a dimension of the contact pad and a second dimension that is greater than a dimension of the contact pad.

Abstract: According to some embodiments, a system, method and non-transitory computer-readable medium are provided comprising an image data source storing image data from a plurality of images; a height map source storing height maps for an area of interest; a building footprint module; a memory storing program instructions; and a building footprint processor, coupled to the memory, and in communication with the building footprint module and operative to execute the program instructions to: receive image data for an area of interest (AOI); receive a height map for the AOI; execute a building segmentation module to generate a building mask that indicates a presence of one or more buildings in the AOI; apply at least one clean mask process to the generated building mask to generate a clean mask; receive the clean mask at an instance building segmentation module; and execute the instance building segmentation module to generate at least one building footprint based on the clean mask and the received image data.

Abstract: A device is provided, including: a first device package including: a first redistribution structure including a first redistribution line and a second redistribution line; a die on the first redistribution structure; a first via coupled to a first side of the first redistribution line; a second via coupled to a first side of the second redistribution line and extending through the second redistribution line; an encapsulant surrounding the die, the first via, and the second via; and a second redistribution structure over the encapsulant, the second redistribution structure electrically connected to the die, the first via, and the second via; a first conductive connector coupled to a second side of the first redistribution line, the first conductive connector disposed along a different axis than a longitudinal axis of the first via; and a second conductive connector coupled to a second side of the second redistribution line, the second conductive connector disposed along a longitudinal axis of the second via.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Abstract: An image sensor device includes a semiconductor substrate, a radiation sensing member, a device layer and a trench isolation. The semiconductor substrate has a front side surface and a back side surface opposite to the front side surface. The radiation sensing member is disposed in a photosensitive region of the semiconductor substrate and extends from the front side surface of the semiconductor substrate. The radiation sensing member includes a semiconductor material with an optical band gap energy smaller than 1.77 eV. The device layer is over the front side surface of the semiconductor substrate and the radiation sensing member. The trench isolation is disposed in an isolation region of the semiconductor substrate and extends from the back side surface of the semiconductor substrate.

Abstract: The present disclosure relates to an integrated chip structure having a first copper pillar disposed over a metal pad of an interposer substrate. The first copper pillar has a sidewall defining a recess. A nickel layer is disposed over the first copper pillar and a solder layer is disposed over the first copper pillar and the nickel layer. The solder layer continuously extends from directly over the first copper pillar to within the recess. A second copper layer is disposed between the solder layer and a second substrate.

Abstract: According to some embodiments, a system, method and non-transitory computer-readable medium are provided comprising a 3D building modeling module; a memory for storing program instructions; a 3D building modeling processor, coupled to the memory, and in communication with the 3D building modeling module and operative to execute program instructions to: receive a region of interest; receive an image of the region of image from a data source; generate a surface model based on the received image including one or more buildings; generate a digital height model; decompose each building into a set of shapes; apply a correction process to the set of shapes; execute a primitive classification process to each shape; execute a fitting process to each classified shape; select a best fitting model; and generate a 3D model of each building. Numerous other aspects are provided.

Abstract: In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.

Abstract: A package-on-package structure includes a first package, a second package and first intermetallic features. The first package includes at least one semiconductor die, an insulating encapsulant, a redistribution layer and conductive pads. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is disposed on the insulating encapsulant. The conductive pads are located at a surface of the insulating encapsulant. The second package is stacked on the first package and electrically connected to the conductive pads through connectors. The first intermetallic features are sandwiched in between the conductive pads and the connectors and have a control region and a growth region. The connectors are connected to the control region, and the growth region spreads out from a periphery of the control region such that the spreading of the growth region extends away from the conductive pads in a direction towards the semiconductor die.

Abstract: A semiconductor structure includes a transceiver, a molding surrounding the transceiver, and a RDL disposed over the transceiver. The RDL includes an antenna and a dielectric layer. The antenna is disposed over and electrically connected to the transceiver. The dielectric layer surrounds the antenna. The antenna includes an elongated portion and a via portion. The elongated portion extends over the molding, and the via portion is electrically connected to the transceiver.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Abstract: A package-on-package structure includes a first package, a second package and first intermetallic features. The first package includes at least one semiconductor die, an insulating encapsulant, a redistribution layer and conductive pads. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is disposed on the insulating encapsulant. The conductive pads are located at a surface of the insulating encapsulant. The second package is stacked on the first package and electrically connected to the conductive pads through connectors. The first intermetallic features are sandwiched in between the conductive pads and the connectors and have a control region and a growth region. The connectors are connected to the control region, and the growth region spreads out from a periphery of the control region such that the spreading of the growth region extends away from the conductive pads in a direction towards the semiconductor die.