Abstract: A memory device includes a substrate, a spin-orbit torque (SOT) layer, a magnetic tunneling junction (MTJ) film stack, a connecting via and a shielding structure. The SOT layer is disposed on the substrate. The MTJ film stack is formed over SOT layer and on the substrate. The connecting via is disposed on and electrically connected to the MTJ film stack. The shielding structure is laterally surrounding the MTJ film stack and disposed on the SOT layer, wherein the shielding structure includes a first dielectric layer, a high magnetic permeability layer and a second dielectric layer, the first dielectric layer is in contact with the SOT layer and the MTJ film stack, and the high magnetic permeability layer is sandwiched between the first dielectric layer and the second dielectric layer.

Abstract: A ferroelectric memory device, a manufacturing method of the ferroelectric memory device and a semiconductor chip are provided. The ferroelectric memory device includes a gate electrode, a ferroelectric layer, a channel layer, first and second blocking layers, and source/drain electrodes. The ferroelectric layer is disposed at a side of the gate electrode. The channel layer is capacitively coupled to the gate electrode through the ferroelectric layer. The first and second blocking layers are disposed between the ferroelectric layer and the channel layer. The second blocking layer is disposed between the first blocking layer and the channel layer. The first and second blocking layers comprise a same material, and the second blocking layer is further incorporated with nitrogen. The source/drain electrodes are disposed at opposite sides of the gate electrode, and electrically connected to the channel layer.

Abstract: The present disclosure relates to an integrated circuit (IC) in which a memory structure comprises a ferroelectric structure without critical-thickness limitations. The memory structure comprises a first electrode and the ferroelectric structure. The ferroelectric structure is vertically stacked with the first electrode and comprises a first ferroelectric layer, a second ferroelectric layer, and a first restoration layer. The second ferroelectric layer overlies the first ferroelectric layer, and the first restoration layer is between and borders the first and second ferroelectric layers. The first restoration layer is a different material type than that of the first and second ferroelectric layers and is configured to decouple crystalline lattices of the first and second ferroelectric layers so the first and second ferroelectric layers do not reach critical thicknesses.

Abstract: The present disclosure relates to an integrated circuit (IC) in which a memory structure comprises a ferroelectric structure without critical-thickness limitations. The memory structure comprises a first electrode and the ferroelectric structure. The ferroelectric structure is vertically stacked with the first electrode and comprises a first ferroelectric layer, a second ferroelectric layer, and a first restoration layer. The second ferroelectric layer overlies the first ferroelectric layer, and the first restoration layer is between and borders the first and second ferroelectric layers. The first restoration layer is a different material type than that of the first and second ferroelectric layers and is configured to decouple crystalline lattices of the first and second ferroelectric layers so the first and second ferroelectric layers do not reach critical thicknesses.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a magnetic tunneling junction (MTJ) and a spin Hall electrode (SHE). The MTJ includes a free layer, a reference layer and a barrier layer lying between the free layer and the reference layer. The SHE is in contact with the MTJ, and configured to convert a charge current to a spin current for programming the MTJ. The SHE is formed of an alloy comprising at least one heavy metal element and at least one light transition metal element. The heavy metal element is selected from metal elements with one or more valence electrons filling in 5d orbitals, and the light transition metal element is selected from transition metal elements with one or more valence electrons partially filling in 3d orbitals.

Abstract: The present invention relates to a composite laminate plate, a housing and a mobile communication device. The composite laminate includes a top metal layer with a through hole and an array antenna, and an area ratio of the array antenna to the through hole meets a specific range, thereby enhancing wave transmissivity of a millimeter wave. Moreover, the composite laminate has a specific material structure, such that it has good mechanical properties and low density. The housing and the mobile communication device made by the composite laminate have advantages of metallic texture, high signal intensity and excellent effect for light weight tendency.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a magnetic tunneling junction (MTJ) and a spin Hall electrode (SHE). The MTJ includes a free layer, a reference layer and a barrier layer lying between the free layer and the reference layer. The SHE is in contact with the MTJ, and configured to convert a charge current to a spin current for programming the MTJ. The SHE is formed of an alloy comprising at least one heavy metal element and at least one light transition metal element. The heavy metal element is selected from metal elements with one or more valence electrons filling in 5 d orbitals, and the light transition metal element is selected from transition metal elements with one or more valence electrons partially filling in 3 d orbitals.

Abstract: Semiconductor device includes pair of active devices, composite spin Hall electrode, and a magnetic tunnel junction. Composite spin Hall electrode is electrically connected to pair of active devices. Magnetic tunnel junction is disposed on opposite side of composite spin hall electrode with respect to pair of active devices. Spin Hall electrode includes pair of heavy metal layers, and spacer layer disposed in between pair of heavy metal layers. Pair of heavy metal layers is made of a heavy metal in a metastable state. Spacer layer comprises first material different from the pair of heavy metal layers.

Abstract: A device includes a substrate having a first side and a second side, a first transistor that includes a first gate over a first protrusion and a first source region and a first drain region interposing the first protrusion, a first buried contact disposed adjacent to the first protrusion and having at least a portion extending into the substrate, a first contact plug disposed over the first drain region, first conductive lines disposed over the first contact plug and electrically connecting to the first drain region by the first contact plug, first via penetrating through the substrate and connecting the first buried contact; and second conductive lines disposed over the second side of the substrate and electrically connecting to the first via. The first buried contact is electrically connecting to the first source region or the first gate.

Abstract: Provided are a memory device and a method of forming the same. The memory device includes: a selector; a magnetic tunnel junction (MTJ) structure, disposed on the selector; a spin orbit torque (SOT) layer, disposed between the selector and the MTJ structure, wherein the SOT layer has a sidewall aligned with a sidewall of the selector; a transistor, wherein the transistor has a drain electrically coupled to the MTJ structure; a word line, electrically coupled to a gate of the transistor; a bit line, electrically coupled to the SOT layer; a first source line, electrically coupled to a source of the transistor; and a second source line, electrically coupled to the selector, wherein the transistor is configured to control a write signal flowing between the bit line and the second source line, and control a read signal flowing between the bit line and the first source line.

Abstract: A device includes a substrate having a first side and a second side, a first transistor that includes a first gate over a first protrusion and a first source region and a first drain region interposing the first protrusion, a first buried contact disposed adjacent to the first protrusion and having at least a portion extending into the substrate, a first contact plug disposed over the first drain region, first conductive lines disposed over the first contact plug and electrically connecting to the first drain region by the first contact plug, first via penetrating through the substrate and connecting the first buried contact; and second conductive lines disposed over the second side of the substrate and electrically connecting to the first via. The first buried contact is electrically connecting to the first source region or the first gate.

Abstract: Provided are a memory device and a method of forming the same. The memory device includes: a selector; a magnetic tunnel junction (MTJ) structure, disposed on the selector; a spin orbit torque (SOT) layer, disposed between the selector and the MTJ structure, wherein the SOT layer has a sidewall aligned with a sidewall of the selector; a transistor, wherein the transistor has a drain electrically coupled to the MTJ structure; a word line, electrically coupled to a gate of the transistor; a bit line, electrically coupled to the SOT layer; a first source line, electrically coupled to a source of the transistor; and a second source line, electrically coupled to the selector, wherein the transistor is configured to control a write signal flowing between the bit line and the second source line, and control a read signal flowing between the bit line and the first source line.

Abstract: A memory device includes a substrate, a spin-orbit torque (SOT) layer, a magnetic tunneling junction (MTJ) film stack, a connecting via and a shielding structure. The SOT layer is disposed on the substrate. The MTJ film stack is formed over SOT layer and on the substrate. The connecting via is disposed on and electrically connected to the MTJ film stack. The shielding structure is laterally surrounding the MTJ film stack and disposed on the SOT layer, wherein the shielding structure includes a first dielectric layer, a high magnetic permeability layer and a second dielectric layer, the first dielectric layer is in contact with the SOT layer and the MTJ film stack, and the high magnetic permeability layer is sandwiched between the first dielectric layer and the second dielectric layer.

Abstract: A memory device is provided. The memory device includes a substrate, a spin-orbit torque layer and a magnetic tunneling junction (MTJ). The MTJ stacks with the spin-orbit torque layer over the substrate and includes a synthetic free layer, a barrier layer and a reference layer. The synthetic free layer includes a synthetic antiferromagnetic structure, a first spacer layer and a free layer, wherein the synthetic antiferromagnetic structure is disposed between the spin-orbit torque layer and the free layer. The barrier layer is disposed beside the synthetic free layer. The reference layer is disposed beside the barrier layer.

Abstract: A memory device including a pair of magnetic conductive posts, a Spin-Hall-Effect-assisted (SHE-assisted) layer, and a magnetic tunneling junction (MTJ) structure. The Spin-Hall-Effect-assisted (SHE-assisted) layer is disposed over and electrically connected to the pair of magnetic conductive posts. The magnetic tunneling junction (MTJ) structure has in-plane magnetic anisotropy, wherein the MTJ structure is disposed on the SHE-assisted layer, and the pair of magnetic conductive posts provide an in-plane magnetic field during a write operation of the MTJ structure.

Abstract: A device includes a substrate having a first side and a second side, a first transistor that includes a first gate over a first protrusion and a first source region and a first drain region interposing the first protrusion, a first buried contact disposed adjacent to the first protrusion and having at least a portion extending into the substrate, a first contact plug disposed over the first drain region, first conductive lines disposed over the first contact plug and electrically connecting to the first drain region by the first contact plug, first via penetrating through the substrate and connecting the first buried contact; and second conductive lines disposed over the second side of the substrate and electrically connecting to the first via. The first buried contact is electrically connecting to the first source region or the first gate.

Abstract: A multilayer plate with composite material and a method thereof are described. The multilayer plate includes an aluminum-based thin sheet and a composite material layer. The aluminum-based thin sheet includes a first passivation layer, an aluminum-based metal layer, and a second passivation layer sequentially. The aluminum-based thin sheet includes a first surface and a second surface opposite to the first surface. The first and second surfaces are set with micro holes. A diameter of the micro holes in the second surface is ranging from 0.5 ?m to 10 ?m. The composite material layer includes a thermoplastic polymer and a fiber material. The composite material layer has a third surface and a fourth surface opposite each other. The second surface is adjacent to or connected to the third surface. At least one portion of the thermoplastic polymer fills into the micro holes in the second surface.

Abstract: A memory device is provided. The memory device includes a substrate, a spin-orbit torque layer and a magnetic tunneling junction (MTJ). The MTJ stacks with the spin-orbit torque layer over the substrate and includes a synthetic free layer, a barrier layer and a reference layer. The synthetic free layer includes a synthetic antiferromagnetic structure, a first spacer layer and a free layer, wherein the synthetic antiferromagnetic structure is disposed between the spin-orbit torque layer and the free layer. The barrier layer is disposed beside the synthetic free layer. The reference layer is disposed beside the barrier layer.

Abstract: Semiconductor device includes pair of active devices, composite spin Hall electrode, and a magnetic tunnel junction. Composite spin Hall electrode is electrically connected to pair of active devices. Magnetic tunnel junction is disposed on opposite side of composite spin hall electrode with respect to pair of active devices. Spin Hall electrode includes pair of heavy metal layers, and spacer layer disposed in between pair of heavy metal layers. Pair of heavy metal layers is made of a heavy metal in a metastable state. Spacer layer comprises first material different from the pair of heavy metal layers.