Patents by Inventor Yen-Ming Chen

Yen-Ming Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200098644
    Abstract: A method of fabricating a fin-like field effect transistor (FinFET) device includes providing a semiconductor substrate having a region for forming p-type metal-oxide-semiconductor (PMOS) devices and a region for forming n-type metal-oxide-semiconductor (PMOS) devices, forming fin structures in both regions of the substrate separated by isolation features, first forming source/drain (S/D) features in the PMOS region, and subsequently forming S/D features in the NMOS region. First forming the PMOS S/D features and then forming the NMOS S/D features results in a greater extent of loss of isolation features in the PMOS region than in the NMOS region.
    Type: Application
    Filed: November 26, 2019
    Publication date: March 26, 2020
    Inventors: Feng-Ching Chu, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20200098886
    Abstract: A semiconductor structure includes a first device and a second device. The first device includes: a first gate structure formed over an active region and a first air spacer disposed adjacent to the first gate structure. The second device includes: a second gate structure formed over an isolation structure and a second air spacer disposed adjacent to the second gate structure. The first air spacer and the second air spacer have different sizes.
    Type: Application
    Filed: July 26, 2019
    Publication date: March 26, 2020
    Inventors: Yi-Hsiu Liu, Feng-Cheng Yang, Tsung-Lin Lee, Wei-Yang Lee, Yen-Ming Chen, Yen-Ting Chen
  • Patent number: 10602301
    Abstract: An audio processing method includes the following steps: receiving audio information; capturing a square wave signal, a white signal, and a speech signal of the audio information; calculating a loudness value of the audio information; calculating a first sound quality value and a second sound quality value of the audio information by using the square wave signal, the white signal, and the speech signal of the audio information; calculating a sound quality level of the audio information by using a first calculation formula, the first calculation formula being the loudness value*[1+(B*the first sound quality value+C*the second sound quality value)], where B and C are respectively values greater than 0 and less than 0.1; and displaying a value of the sound quality level of the audio information.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: March 24, 2020
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Yao-Jen Liu, Yen-Ming Chen, Wei-Lun Chen, Tsung-Yen Yu, Chin-Chuan Lee, Guan-De Kuo, Shao-Hsiang Chen
  • Publication number: 20200075420
    Abstract: Various examples of an integrated circuit with a sidewall spacer and a technique for forming an integrated circuit with such a spacer are disclosed herein. In some examples, the method includes receiving a workpiece that includes a substrate and a gate stack disposed upon the substrate. A spacer is formed on a side surface of the gate stack that includes a spacer layer with a low-k dielectric material. A source/drain region is formed in the substrate; and a source/drain contact is formed coupled to the source/drain region such that the spacer layer of the spacer is disposed between the source/drain contact and the gate stack.
    Type: Application
    Filed: November 8, 2019
    Publication date: March 5, 2020
    Inventors: Yen-Ting Chen, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20200075417
    Abstract: A method is provided for forming a device. The method includes forming a trench that exposes a source/drain (S/D) feature, wherein the S/D feature is separated from a metal gate structure (MG) by a gate spacer. The method further includes removing the gate spacer to form an air gap and forming a first dielectric layer in the trench, wherein the first dielectric layer partially fills the air gap. The method also includes forming a second dielectric layer over the first dielectric layer in the trench and forming a S/D contact over the S/D feature and the second dielectric layer, wherein the second dielectric layer is different from the first dielectric layer. After forming the S/D contact, the first dielectric layer is removed to extend the air gap; and after removing the first dielectric layer, a third dielectric layer is formed to seal the air gap.
    Type: Application
    Filed: April 30, 2019
    Publication date: March 5, 2020
    Inventors: Kai-Hsuan Lee, Feng-Cheng Yang, Yen-Ming Chen, Sai-Hooi Yeong
  • Publication number: 20200066734
    Abstract: A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.
    Type: Application
    Filed: October 31, 2019
    Publication date: February 27, 2020
    Inventors: Kai-Hsuan Lee, Chia-Ta Yu, Cheng-Yu Yang, Sheng-Chen Wang, Sai-Hooi Yeong, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20200043804
    Abstract: A fin structure of a FinFET device is formed over a substrate. A first layer is formed over the fin structure. A gate layer is formed over the fin structure and over the first layer. The gate layer is patterned into a gate stack that wraps around the fin structure. A second layer is formed over the first layer and over the gate stack. A first etching process is performed to remove portions of the second layer formed over the fin structure, the first layer serves as an etching-stop layer during the first etching process. A second etching process is performed to remove portions of the first layer to expose a portion of the fin structure. A removal of the portions of the first layer does not substantially affect the second layer. A source/drain region is epitaxially grown on the exposed portion of the fin structure.
    Type: Application
    Filed: October 11, 2019
    Publication date: February 6, 2020
    Inventors: Yen-Ting Chen, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20200035780
    Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a substrate, and the substrate includes a capacitor region and a non-capacitor region. The MIM capacitor structure includes a first electrode layer formed over the substrate, and a first spacer formed on a sidewall of the first electrode layer. The MIM capacitor structure includes a first dielectric layer formed on the first spacers, and a second electrode layer formed on the first dielectric layer. The second electrode layer extends from the capacitor region to the non-capacitor region, and the second electrode layer extends beyond an outer sidewall of the first spacer.
    Type: Application
    Filed: October 4, 2019
    Publication date: January 30, 2020
    Inventors: Chih-Fan HUANG, Chih-Yang PAI, Yuan-Yang HSIAO, Tsung-Chieh HSIAO, Hui-Chi CHEN, Dian-Hau CHEN, Yen-Ming CHEN
  • Publication number: 20200035779
    Abstract: A metal-insulator-metal (MIM) capacitor structure includes a semiconductor substrate and a bottom conductive layer above the semiconductor substrate. The bottom conductive layer has a slanted sidewall with respect to a top surface of the semiconductor substrate. The MIM capacitor structure further includes a top conductive layer above the bottom conductive layer. The top conductive layer has a vertical sidewall with respect to the top surface of the semiconductor substrate. The MIM capacitor structure further includes an insulating layer interposed between the bottom conductive layer and the top conductive layer. The insulating layer covers the slanted sidewall of the bottom conductive layer.
    Type: Application
    Filed: October 10, 2018
    Publication date: January 30, 2020
    Inventors: Chih-Fan Huang, Hung-Chao Kao, Yuan-Yang Hsiao, Tsung-Chieh Hsiao, Hsiang-Ku Shen, Hui-Chi Chen, Dian-Hau Chen, Yen-Ming Chen
  • Publication number: 20200020807
    Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.
    Type: Application
    Filed: May 16, 2019
    Publication date: January 16, 2020
    Inventors: Wei-Jen Lai, Yen-Ming Chen, Tsung-Lin Lee
  • Patent number: 10535569
    Abstract: A method includes forming a gate dielectric layer on a semiconductor fin, and forming a gate electrode over the gate dielectric layer. The gate electrode extends on sidewalls and a top surface of the semiconductor fin. A gate spacer is selectively deposited on a sidewall of the gate electrode. An exposed portion of the gate dielectric layer is free from a same material for forming the gate spacer deposited thereon. The method further includes etching the gate dielectric layer using the gate spacer as an etching mask to expose a portion of the semiconductor fin, and forming an epitaxy semiconductor region based on the semiconductor fin.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Hsuan Lee, Chia-Ta Yu, Cheng-Yu Yang, Sheng-Chen Wang, Bo-Yu Lai, Bo-Cyuan Lu, Chi On Chui, Sai-Hooi Yeong, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20200013779
    Abstract: A method of forming a semiconductor device includes etching a substrate to form two first trenches separated by a fin; filling the two first trenches with an isolation layer; and depositing a dielectric layer over the fin and the isolation layer. The method further includes forming a second trench in the dielectric layer over a channel region of the semiconductor device, the second trench exposing the isolation layer. The method further includes etching the isolation layer through the second trench to expose an upper portion of the fin in the channel region of the semiconductor device, and forming a dummy gate in the second trench over the isolation layer and engaging the upper portion of the fin.
    Type: Application
    Filed: September 16, 2019
    Publication date: January 9, 2020
    Inventors: Hung-Li Chiang, Cheng-Yi Peng, Tsung-Yao Wen, Yee-Chia Yeo, Yen-Ming Chen
  • Patent number: 10529725
    Abstract: A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: January 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Hsuan Lee, Chia-Ta Yu, Cheng-Yu Yang, Sheng-Chen Wang, Sai-Hooi Yeong, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 10529803
    Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. In some embodiments, the semiconductor device includes a fin extending from a substrate and a gate structure disposed over the fin. The gate structure includes a gate dielectric formed over the fin, a gate electrode formed over the gate dielectric, and a sidewall spacer formed along a sidewall of the gate electrode. In some cases, a U-shaped recess is within the fin and adjacent to the gate structure. A first source/drain layer is conformally formed on a surface of the U-shaped recess, where the first source/drain layer extends at least partially under the adjacent gate structure. A second source/drain layer is formed over the first source/drain layer. At least one of the first and second source/drain layers includes silicon arsenide (SiAs).
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: January 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ta Yu, Sheng-Chen Wang, Wei-Yuan Lu, Chien-I Kuo, Li-Li Su, Feng-Cheng Yang, Yen-Ming Chen, Sai-Hooi Yeong
  • Publication number: 20200006183
    Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method for integrated circuit (IC) fabrication includes forming a passivation layer over a first contact feature, forming a second contact feature over and through the passivation layer to electrically connect to the first contact feature, and forming a multi-layer passivation structure over the second contact feature and over the passivation layer. Forming the multi-layer passivation structure includes depositing a first nitride layer, an oxide layer over the first nitride layer, and a second nitride layer over the oxide layer.
    Type: Application
    Filed: April 26, 2019
    Publication date: January 2, 2020
    Inventors: Chih-Fan Huang, Hui-Chi Chen, Kuo-Chin Chang, Dian-Hau Chen, Yen-Ming Chen
  • Publication number: 20200006158
    Abstract: A method includes providing dummy gate structures disposed over a device region and over an isolation region adjacent the active region, first gate spacers disposed along sidewalls of the dummy gate structures in the active region, and second gate spacers disposed along sidewalls of the dummy gate structures in the isolation region, removing top portions of the second, but not the first gate spacers, forming a first dielectric layer over the first gate spacers and remaining portions of the second gate spacers, replacing the dummy gate structures with metal gate structures after the forming of the first dielectric layer, removing the first gate spacers after the replacing of the dummy gate structures, and forming a second dielectric layer over top surfaces of the metal gate structures and of the first dielectric layer.
    Type: Application
    Filed: December 12, 2018
    Publication date: January 2, 2020
    Inventors: Yen-Ting Chen, Yi-Hsiu Liu, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20200006084
    Abstract: A semiconductor device is provided. The semiconductor device has a fin structure that protrudes vertically upwards. A lateral dimension of the fin structure is reduced. A semiconductor layer is formed on the fin structure after the reducing of the lateral dimension. An annealing process is performed to the semiconductor device after the forming of the semiconductor layer. A dielectric layer is formed over the fin structure after the performing of the annealing process.
    Type: Application
    Filed: October 12, 2018
    Publication date: January 2, 2020
    Inventors: Tzung-Yi Tsai, Yen-Ming Chen, Tsung-Lin Lee, Po-Kang Ho
  • Patent number: 10522680
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a first fin structure over the base. The semiconductor device structure includes an isolation layer over the base. The first fin structure is partially in the isolation layer. The semiconductor device structure includes a first gate structure over and across the first fin structure. The semiconductor device structure includes a first source structure and a first drain structure on the first fin structure and on two opposite sides of the first gate structure. The first source structure and the first drain structure are made of an N-type conductivity material. The semiconductor device structure includes a cap layer covering the first source structure and the first drain structure. The cap layer is doped with a Group IIIA element.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Ching Chu, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 10522420
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a first device region and a second device region, a first fin over the substrate in the first device region, a second fin over the substrate in the second device region, a first epitaxial feature over the first fin in the source/drain region of the first fin, a second epitaxial feature over the second fin in the source/drain region of the second fin, and a dielectric layer on the first and second epitaxial features. The first epitaxial feature is doped with a first dopant of a first conductivity and the second epitaxial feature is doped with a second dopant of a second conductivity different from the first conductivity. The dielectric layer is doped with the first dopant.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Ching Chu, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 10522642
    Abstract: A method includes forming a gate structure on a substrate, forming a seal spacer covering a sidewall of the gate structure, forming a sacrificial spacer covering a sidewall of the seal spacer, forming source/drain regions sandwiching a channel region that is under the gate structure, and depositing a contact etch stop layer covering a sidewall of the sacrificial spacer. The method further includes removing the sacrificial spacer to form a trench, wherein the trench exposes a sidewall of the contact etch stop layer and the sidewall of the seal spacer, and depositing an inter-layer dielectric layer, wherein the inter-layer dielectric layer caps the trench, thereby defining an air gap inside the trench.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.
    Inventors: Wei-Yang Lee, Feng-Cheng Yang, Chung-Te Lin, Yen-Ming Chen