Abstract: A semiconductor device includes a memory region including an array of memory cell devices, and a test region including a test memory cell structure. The test memory cell structure includes a first gate stack on a first raised portion of a substrate, a first polysilicon structure adjacent to the first raised portion and in a region between the first raised portion and a second raised portion of the substrate, a first spacer adjacent to the first polysilicon structure, and a second gate stack on the second raised portion, a second polysilicon structure adjacent to the second raised portion and in the region between the first raised portion and the second raised portion, and a second spacer adjacent to the second polysilicon structure. The semiconductor device includes an interlayer dielectric layer over at least a portion of the memory region and at least a portion of the test region.

Abstract: The invention is to provide a centralized computer system, i.e., the so-called blade PC system. The centralized computer system according to the invention includes a plurality of centralized and bladed hosts. In particularly, the centralized computer system according to the invention enables two sets of I/O peripherals to operate the same host in a hardware-driven way.