Patents by Inventor Yen-Ping Wang

Yen-Ping Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150118797
    Abstract: A method of packaging an integrated circuit includes forming a first integrated circuit and a second integrated circuit on a wafer, the first and second integrated circuit separated by a singulation region. The method includes covering the first and second integrated circuits with a molding compound, and sawing through a top portion of the molding compound using a first beveled saw blade, while leaving a bottom portion of the molding compound remaining. The method further includes sawing through the bottom portion of the molding compound and the wafer using a second saw blade, the second saw blade having a thickness that is less than a thickness of the first saw blade. The resulting structure is within the scope of the present disclosure.
    Type: Application
    Filed: October 30, 2013
    Publication date: April 30, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Kai Liu, Yen-Ping Wang, Kai-Chiang Wu
  • Publication number: 20150061116
    Abstract: A semiconductor device includes a carrier, an under bump metallurgy (UBM) pad on the carrier, and a post on a surface of the UBM pad. In some embodiments, a height of the post to a longest length of the UBM pad is between about 0.25 and about 0.7. A method of manufacturing a semiconductor device includes providing a carrier, disposing a UBM pad on the carrier and forming a post on the UBM pad.
    Type: Application
    Filed: August 29, 2013
    Publication date: March 5, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: CHUN-LIN LU, KAI-CHIANG WU, MING-KAI LIU, YEN-PING WANG, SHIH-WEI LIANG, CHING-FENG YANG, CHIA-CHUN MIAO, HAO-YI TSAI
  • Publication number: 20150035161
    Abstract: A singulated semiconductor structure comprises a molding compound; a first conductive post in the molding compound having a first geometric shape in a top view; a second conductive post or an alignment mark in the molding compound having a second geometric shape in a top view, wherein the second geometric shape is different from the first geometric shape. The second conductive post or an alignment mark can be positioned at the corner, the center, the edge, or the periphery of the singulated semiconductor structure. The second geometric shape can be any geometric construct distinguishable from the first geometric shape. The second conductive post or an alignment mark can be placed at an active area or a non-active area of the singulated semiconductor structure.
    Type: Application
    Filed: July 30, 2013
    Publication date: February 5, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: CHIA-CHUN MIAO, SHIH-WEI LIANG, KAI-CHIANG WU, MING-KAI LIU, YEN-PING WANG
  • Publication number: 20150008575
    Abstract: A surface mounting semiconductor component includes a semiconductor device, a circuit board, a number of first solder bumps, and a number of second solder bumps. The semiconductor device included a number of die pads. The circuit board includes a number of contact pads. The first solder bumps are configured to bond the semiconductor device and the circuit board. Each of the first solder bumps connects at least two die pads with a corresponding contact pad. Each of the second solder bumps connects a die pad with a corresponding contact pad. A method of forming a surface mounting component or a chip scale package assembly wherein the component or assembly has at least two different types of solder bumps.
    Type: Application
    Filed: July 3, 2013
    Publication date: January 8, 2015
    Inventors: MING-KAI LIU, CHUN-LIN LU, KAI-CHIANG WU, SHIH-WEI LIANG, CHING-FENG YANG, YEN-PING WANG, CHIA-CHUN MIAO
  • Publication number: 20150001704
    Abstract: Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.
    Type: Application
    Filed: June 26, 2013
    Publication date: January 1, 2015
    Inventors: Chun-Lin LU, Kai-Chiang WU, Ming-Kai LIU, Yen-Ping WANG, Shih-Wei LIANG, Ching-Feng YANG, Chia-Chun MIAO, Hung-Jen LIN
  • Publication number: 20140252657
    Abstract: An embodiment is a semiconductor device comprising a first bond pad on a first substrate, the first bond pad having a first center line through a center of the first bond pad and orthogonal to a top surface of the first substrate, and a first conductive connector on a second substrate, the first conductive connector having a second center line through a center of the first conductive connector and orthogonal to a top surface of the second substrate, the second substrate over the first substrate with the top surface of the first substrate facing the top surface of the second substrate. The semiconductor device further comprises a first alignment component adjacent the first bond pad on the first substrate, the first alignment component configured to align the first center line with the second center line.
    Type: Application
    Filed: March 6, 2013
    Publication date: September 11, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Kai Liu, Chia-Chun Miao, Kai-Chiang Wu, Shih-Wei Liang, Ching-Feng Yang, Yen-Ping Wang, Chun-Lin Lu
  • Patent number: 8759185
    Abstract: A MOSFET includes a gate having a high-k gate dielectric on a substrate and a gate electrode on the gate dielectric. The gate dielectric protrudes beyond the gate electrode. A deep source and drain having shallow extensions are formed on either side of the gate. The deep source and drain are formed by selective in-situ doped epitaxy or by ion implantation and the extensions are formed by selective, in-situ doped epitaxy. The extensions lie beneath the gate in contact with the gate dielectric. The material of the gate dielectric and the amount of its protrusion beyond the gate electrode are selected so that epitaxial procedures and related procedures do not cause bridging between the gate electrode and the source/drain extensions. Methods of fabricating the MOSFET are described.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: June 24, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Wang, Shang-Chih Chen, Yen-Ping Wang, Hsien-Kuang Chiu, Liang-Gi Yao, Chenming Hu
  • Publication number: 20140160688
    Abstract: Methods and apparatus for an interposer with a dam used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.
    Type: Application
    Filed: December 6, 2012
    Publication date: June 12, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Lin Lu, Kai-Chiang Wu, Yen-Ping Wang, Shih-Wei Liang, Ching-Feng Yang
  • Publication number: 20140125385
    Abstract: A level shifter capable of pulse filtering and a bridge driver using the same, the level shifter capable of pulse filtering being used for up shifting a first clock signal and a second clock signal to provide a set signal and a reset signal, and for preventing noise on the first clock signal or on the second clock signal from altering the states of the set signal and the reset signal.
    Type: Application
    Filed: January 10, 2014
    Publication date: May 8, 2014
    Applicant: Alitek Technology Corp.
    Inventor: Yen-Ping Wang
  • Publication number: 20140117555
    Abstract: An integrated circuit includes a substrate having at least one depression on a top surface. At least one solder bump is disposed over the substrate. A die is disposed over the at least one solder bump and electrically connected with the substrate through the at least one solder bump. An underfill surrounds the at least one solder bump and is formed between the substrate and the die. The at least one depression is disposed around the underfill to keep any spillover from the underfill in the at least one depression.
    Type: Application
    Filed: December 21, 2012
    Publication date: May 1, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Wei Liang, Chun-Lin Lu, Kai-Chiang Wu, Ching-Feng Yang, Ming-Kai Liu, Chia-Chun Miao, Yen-Ping Wang
  • Publication number: 20140002140
    Abstract: A level shifter capable of pulse filtering and a bridge driver using the same, the level shifter capable of pulse filtering being used for up shifting a first clock signal and a second clock signal to provide a set signal and a reset signal, and for preventing noise on the first clock signal or on the second clock signal from altering the states of the set signal and the reset signal.
    Type: Application
    Filed: June 28, 2012
    Publication date: January 2, 2014
    Inventor: Yen-Ping Wang
  • Patent number: 8603911
    Abstract: A semiconductor structure includes a chip, a plurality of metal posts disposed in the chip and a buffer layer disposed on the chip. The chip includes a silicon-based layer having opposite first and second surfaces, and a build-up structure formed on the first surface of the silicon-based layer consisting of at least a metal layer and a low-k dielectric layer alternatively stacked on one another. Each of the metal posts is disposed in the silicon-based layer with one end thereof electrically connected with the metal layer while the other end is exposed from the second surface of the silicon-based layer. The buffer layer is disposed on the build-up structure. By positioning the low-k dielectric layer far from the second surface that is used for connecting to an external electronic component, the present invention reduces the overall thermal stress.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: December 10, 2013
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Hui-Min Huang, Chun-Tang Lin, Chien-Wei Lee, Yen-Ping Wang
  • Publication number: 20130285626
    Abstract: A DC-DC converter is provided. The DC-DC converter a power stage includes a first high side driver and a protecting circuit including a second high side driver, wherein the first high side driver and the second high side driver are connected in parallel, and operate in complementary.
    Type: Application
    Filed: April 27, 2012
    Publication date: October 31, 2013
    Applicant: ALITEK TECHNOLOGY CORP.
    Inventors: Yu-Jung Chen, Yen-Ping Wang
  • Patent number: 8564363
    Abstract: A pulse filter and a bridge driver using the same, the pulse filter including: a first NMOS transistor, having a drain coupled to a first PMOS transistor for providing a reset signal, a gate coupled to a second reset signal, and a source coupled to a second set signal; a second NMOS transistor, having a drain coupled to a second PMOS transistor for providing a set signal, a gate coupled to the second set signal, and a source coupled to the second reset signal; a third NMOS transistor, having a drain coupled to the second set signal, a gate coupled to the second reset signal, and a source coupled to a second power line; and a fourth NMOS transistor, having a drain coupled to the second reset signal, a gate coupled to the second set signal, and a source coupled to the second power line.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: October 22, 2013
    Assignee: Alitek Technology Corp.
    Inventor: Yen-Ping Wang
  • Patent number: 8450940
    Abstract: A gas-discharge lamp controller utilizing a novel preheating phase control mechanism, having: a supply voltage tracking reference voltages generator, biased between a supply voltage and a reference ground, for generating a first reference voltage which is proportional to the supply voltage; and a control unit, for generating a high threshold signal according to the first reference voltage and a saw-tooth signal, the peak value of the saw-tooth signal being proportional to the supply voltage, wherein the control unit has a preheating phase, the high threshold signal is coupled with the first reference voltage during the preheating phase, and the time duration of the preheating phase is set by a predetermined number of periods of the saw-tooth signal.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: May 28, 2013
    Assignee: Grenergy Opto Inc.
    Inventors: Yen-Ping Wang, Pei-Yuan Chen, Ko-Ming Lin
  • Patent number: 8304665
    Abstract: A package substrate having landless conductive traces is proposed, which includes a core layer with a plurality of plated through holes formed therein, and a plurality of conductive traces formed on at least a surface of the core layer. Each of the conductive traces has a connection end, a bond pad end, and a base body connecting the connection end and the bond pad end, the conductive trace is electrically connected to a corresponding one of the plated through holes through the connection end, and the connection end has a width greater than that of the base body but not greater than the diameter of the plated through hole, thereby increasing the contact area between the conductive trace and the plated through hole and preventing the contact surface of the conductive trace with the plated through hole from cracking.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: November 6, 2012
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chiang-Cheng Chang, Yen-Ping Wang, Don-Son Jiang, Jeng-Yuan Lai, Yu-Po Wang
  • Publication number: 20120223425
    Abstract: A semiconductor structure includes a chip, a plurality of metal posts disposed in the chip and a buffer layer disposed on the chip. The chip includes a silicon-based layer having opposite first and second surfaces, and a build-up structure formed on the first surface of the silicon-based layer consisting of at least a metal layer and a low-k dielectric layer alternatively stacked on one another. Each of the metal posts is disposed in the silicon-based layer with one end thereof electrically connected with the metal layer while the other end is exposed from the second surface of the silicon-based layer. The buffer layer is disposed on the build-up structure. By positioning the low-k dielectric layer far from the second surface that is used for connecting to an external electronic component, the present invention reduces the overall thermal stress.
    Type: Application
    Filed: May 11, 2011
    Publication date: September 6, 2012
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Hui-Min Huang, Chun-Tang Lin, Chien-Wei Lee, Yen-Ping Wang
  • Patent number: 8217583
    Abstract: A gas-discharge lamp controller utilizing a novel preheating frequency generation mechanism, including: a resistance sensing means, used to generate a sensed voltage when coupled to an external series resistor-capacitor network, the external series resistor-capacitor network being biased between a first supply voltage and a reference ground; a sample and hold circuit, used to generate a sampled voltage of the sensed voltage under the control of a latch signal; and a mapping circuit, used to generate a control voltage according to a function of the sampled voltage.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: July 10, 2012
    Assignee: Grenergy Opto, Inc.
    Inventors: Yen-Ping Wang, Ko-Ming Lin
  • Publication number: 20120083076
    Abstract: A MOSFET includes a gate having a high-k gate dielectric on a substrate and a gate electrode on the gate dielectric. The gate dielectric protrudes beyond the gate electrode. A deep source and drain having shallow extensions are formed on either side of the gate. The deep source and drain are formed by selective in-situ doped epitaxy or by ion implantation and the extensions are formed by selective, in-situ doped epitaxy. The extensions lie beneath the gate in contact with the gate dielectric. The material of the gate dielectric and the amount of its protrusion beyond the gate electrode are selected so that epitaxial procedures and related procedures do not cause bridging between the gate electrode and the source/drain extensions. Methods of fabricating the MOSFET are described.
    Type: Application
    Filed: December 13, 2011
    Publication date: April 5, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Wang, Shang-Chih Chen, Yen-Ping Wang, Hsien-Kuang Chiu, Liang-Gi Yao, Chenming Hu
  • Publication number: 20120019159
    Abstract: A gas-discharge lamp controller utilizing a novel preheating frequency generation mechanism, including: a resistance sensing means, used to generate a sensed voltage when coupled to an external series resistor-capacitor network, the external series resistor-capacitor network being biased between a first supply voltage and a reference ground; a sample and hold circuit, used to generate a sampled voltage of the sensed voltage under the control of a latch signal; and a mapping circuit, used to generate a control voltage according to a function of the sampled voltage.
    Type: Application
    Filed: July 21, 2010
    Publication date: January 26, 2012
    Inventors: Yen-Ping Wang, Ko-Ming Lin