Patents by Inventor Yen-Wen Lu

Yen-Wen Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140359543
    Abstract: Described herein is a method for obtaining a preferred layout for a lithographic process, the method comprising: identifying an initial layout including a plurality of features; and reconfiguring the features until a termination condition is satisfied, thereby obtaining the preferred layout; wherein the reconfiguring comprises evaluating a cost function that measures how a lithographic metric is affected by a set of changes to the features for a plurality of lithographic process conditions, and expanding the cost function into a series of terms at least some of which are functions of characteristics of the features.
    Type: Application
    Filed: August 18, 2014
    Publication date: December 4, 2014
    Applicant: ASML Netherlands B.V.
    Inventors: Jun TAO, Been-Der Chen, Yen-Wen Lu, Jiangwei Li, Min-Chun Tsai, Dong Mao
  • Publication number: 20140351772
    Abstract: Described herein is a method of processing a pattern layout for a lithographic process, the method comprising: identifying a feature from a plurality of features of the layout, the feature violating a pattern layout requirement; and reconfiguring the feature, wherein the reconfigured feature still violates the pattern layout requirement, the reconfiguring including evaluating a cost function that measures a lithographic metric affected by a change to the feature and a parameter characteristic of relaxation of the pattern layout requirement.
    Type: Application
    Filed: August 11, 2014
    Publication date: November 27, 2014
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Taihui LIU, Been-Der CHEN, Yen-Wen LU
  • Patent number: 8893067
    Abstract: In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: November 18, 2014
    Assignee: ASML Netherlands B.V.
    Inventors: Jun Ye, Yen-Wen Lu, Yu Cao, Luoqi Chen, Xun Chen
  • Patent number: 8826198
    Abstract: Model-Based Sub-Resolution Assist Feature (SRAF) generation process and apparatus are disclosed, in which an SRAF guidance map (SGM) is iteratively optimized to finally output an optimized set of SRAFs as a result of enhanced signal strength obtained by iterations involving SRAF polygons and SGM image. SRAFs generated in a prior round of iteration are incorporated in a mask layout to generate a subsequent set of SRAFs. The iterative process is terminated when a set of SRAF accommodates a desired process window or when a predefined process window criterion is satisfied. Various cost functions, representing various lithographic responses, may be predefined for the optimization process.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: September 2, 2014
    Assignee: ASML Netherlands B.V.
    Inventors: Min-Chun Tsai, Been-Der Chen, Yen-Wen Lu
  • Patent number: 8812998
    Abstract: Described herein is a method for obtaining a preferred layout for a lithographic process, the method comprising: identifying an initial layout including a plurality of features; and reconfiguring the features until a termination condition is satisfied, thereby obtaining the preferred layout; wherein the reconfiguring comprises evaluating a cost function that measures how a lithographic metric is affected by a set of changes to the features for a plurality of lithographic process conditions, and expanding the cost function into a series of terms at least some of which are functions of characteristics of the features.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: August 19, 2014
    Assignee: ASML Netherlands B.V.
    Inventors: Jun Tao, Been-Der Chen, Yen-Wen Lu, Jiangwei Li, Min-Chun Tsai, Dong Mao
  • Patent number: 8806389
    Abstract: Described herein is a method of processing a pattern layout for a lithographic process, the method comprising: identifying a feature from a plurality of features of the layout, the feature violating a pattern layout requirement; and reconfiguring the feature, wherein the reconfigured feature still violates the pattern layout requirement, the reconfiguring including evaluating a cost function that measures a lithographic metric affected by a change to the feature and a parameter characteristic of relaxation of the pattern layout requirement.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: August 12, 2014
    Assignee: ASML Netherlands B.V.
    Inventors: Taihui Liu, Been-Der Chen, Yen-Wen Lu
  • Patent number: 8739082
    Abstract: The present invention relates to a method of selecting a subset of patterns from a design, to a method of performing source and mask optimization, and to a computer program product for performing the method of selecting a subset of patterns from a design. According to certain aspects, the present invention enables coverage of the full design while lowering the computation cost by intelligently selecting a subset of patterns from a design in which the design or a modification of the design is configured to be imaged onto a substrate via a lithographic process. The method of selecting the subset of patterns from a design includes identifying a set of patterns from the design related to the predefined representation of the design. By selecting the subset of patterns according to the method, the selected subset of patterns constitutes a similar predefined representation of the design as the set of patterns.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: May 27, 2014
    Inventors: Hua-Yu Liu, Luoqi Chen, Hong Chen, Zhi-Pan Li, Jun Ye, Min-Chun Tsai, Youping Zhang, Yen-Wen Lu, Jiangwei Li
  • Publication number: 20140080722
    Abstract: The present invention provides a method of SNP detection by using DASH technique in bead-based microfluidics comprising following steps: (a) immobilizing a target single-strand DNA onto a microbead; (b) hybridizing the target single-strand DNA with an allele-specific probe; (c) intercalating a dye into a target-probe duplex region; (d) delivering the microbead into a microchannel; (e) heating the microbead to denature a hybridized DNA obtained from the step (c); (f) monitoring a fluorescence intensity of the hybridized DNA during the step (e) to obtain a melting curve; and (g) determining the SNP by a melting curve analysis method. Also, the present invention offers a rapid genotyping detection scheme with minimal amount of the reagents by confining the microbeads into designed fluidic traps and performing melting curve analysis controlled by a temperature control platform. The trapping mechanism was validated and optimized.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Applicant: NATIONAL TAIWAN UNIVERSITY
    Inventors: Pei-Chun KAO, Shih-Throng DING, En-Chung LIN, Yen-Wen LU
  • Publication number: 20130332894
    Abstract: In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques.
    Type: Application
    Filed: August 20, 2013
    Publication date: December 12, 2013
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Jun YE, Yen-Wen LU, Yu CAO
  • Publication number: 20130311959
    Abstract: The method of the invention tracks how the collective movement of edge segments in a mask layout alters the resist image values at control points in the layout and simultaneously determines a correction amount for each edge segment in the layout. A multisolver matrix that represents the collective effect of movements of each edge segment in the mask layout is used to simultaneously determine the correction amount for each edge segment in the mask layout.
    Type: Application
    Filed: May 17, 2013
    Publication date: November 21, 2013
    Applicant: ASML NETHERLANDS B.V.
    Inventors: William S. WONG, Been-Der CHEN, Yen-Wen LU, Jiangwei LI, Tatsuo NISHIBE
  • Publication number: 20130311960
    Abstract: Model-Based Sub-Resolution Assist Feature (SRAF) generation process and apparatus are disclosed, in which an SRAF guidance map (SGM) is iteratively optimized to finally output an optimized set of SRAFs as a result of enhanced signal strength obtained by iterations involving SRAF polygons and SGM image. SRAFs generated in a prior round of iteration are incorporated in a mask layout to generate a subsequent set of SRAFs. The iterative process is terminated when a set of SRAF accommodates a desired process window or when a predefined process window criterion is satisfied. Various cost functions, representing various lithographic responses, may be predefined for the optimization process.
    Type: Application
    Filed: May 13, 2013
    Publication date: November 21, 2013
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Min-Chun Tsai, Been-Der Chen, Yen-Wen Lu
  • Patent number: 8560979
    Abstract: A multivariable solver for proximity correction uses a Jacobian matrix to approximate effects of perturbations of segment locations in successive iterations of a design loop. The problem is formulated as a constrained minimization problem with box, linear equality, and linear inequality constraints. To improve computational efficiency, non-local interactions are ignored, which results in a sparse Jacobian matrix.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: October 15, 2013
    Assignee: ASML Netherlands B.V.
    Inventors: William S. Wong, Fei Liu, Been-Der Chen, Yen-Wen Lu
  • Patent number: 8516405
    Abstract: In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: August 20, 2013
    Assignee: ASML Netherlands B.V.
    Inventors: Jun Ye, Yen-Wen Lu, Yu Cao, Luoqi Chen, Xun Chen
  • Patent number: 8448099
    Abstract: The method of the invention tracks how the collective movement of edge segments in a mask layout alters the resist image values at control points in the layout and simultaneously determines a correction amount for each edge segment in the layout. A multisolver matrix that represents the collective effect of movements of each edge segment in the mask layout is used to simultaneously determine the correction amount for each edge segment in the mask layout.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: May 21, 2013
    Assignee: ASML Netherlands B.V.
    Inventors: William S. Wong, Been-Der Chen, Yen-Wen Lu, Jiangwei Li, Tatsuo Nishibe
  • Patent number: 8443312
    Abstract: Model-Based Sub-Resolution Assist Feature (SRAF) generation process and apparatus are disclosed, in which an SRAF guidance map (SGM) is iteratively optimized to finally output an optimized set of SRAFs as a result of enhanced signal strength obtained by iterations involving SRAF polygons and SGM image. SRAFs generated in a prior round of iteration are incorporated in a mask layout to generate a subsequent set of SRAFs. The iterative process is terminated when a set of SRAF accommodates a desired process window or when a predefined process window criterion is satisfied. Various cost functions, representing various lithographic responses, may be predefined for the optimization process.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: May 14, 2013
    Assignee: ASML Netherlands B.V.
    Inventors: Min-Chun Tsai, Been-Der Chen, Yen-Wen Lu
  • Publication number: 20130063012
    Abstract: A drawer cart with in-mold labels includes a cart and a plurality of drawers made by injection molding. Each drawer has a housing compartment opened upward and a display surface. The drawers are slidably mounted onto the cart with the display surfaces exposed outwards and can be partially drawn away from the cart to expose the housing compartment. The display surface contains an in-mold label formed during the injection molding. The in-mold label has patterns for indication and visual aesthetic, and also facilitating classification of goods held in the drawers. The patterns on the in-mold label can be designed differently in response to varying display surfaces and can be combined to form a whole pattern to enhance total design sense and meet use requirements.
    Type: Application
    Filed: May 31, 2012
    Publication date: March 14, 2013
    Inventor: Yen-Wen Lu
  • Patent number: D685805
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: July 9, 2013
    Assignee: Compal Electronics, Inc.
    Inventors: Yen-Wen Lu, Chia-Chen Yang
  • Patent number: D690674
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: October 1, 2013
    Assignee: Compal Electronics, Inc.
    Inventors: Yen-Wen Lu, Hao-Jen Chang
  • Patent number: D694235
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: November 26, 2013
    Assignee: Compal Electronics, Inc.
    Inventors: Yen-Wen Lu, Kuei-Min Pan
  • Patent number: D699203
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: February 11, 2014
    Assignee: Compal Electronics, Inc.
    Inventors: Yen-Wen Lu, Kuei-Min Pan