Patents by Inventor Yeong-Jyh Lin

Yeong-Jyh Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10513070
    Abstract: A method includes placing a package structure into a mold chase, with top surfaces of device dies in the package structure contacting a release film in the mold chase. A molding compound is injected into an inner space of the mold chase through an injection port, with the injection port on a side of the mold chase. During the injection of the molding compound, a venting step is performed through a first venting port and a second venting port of the mold chase. The first venting port has a first flow rate, and the second port has a second flow rate different from the first flow rate.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bor-Ping Jang, Yeong-Jyh Lin, Chien Ling Hwang, Chung-Shi Liu, Meng-Tse Chen, Ming-Da Cheng, Chen-Hua Yu
  • Patent number: 10510712
    Abstract: A method includes placing a plurality of dummy dies over a carrier, placing a plurality of device dies over the carrier, molding the plurality of dummy dies and the plurality of device dies in a molding compound, forming redistribution line over and electrically coupled to the device dies, and performing a die-saw to separate the device dies and the molding compound into a plurality of packages.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Bor-Ping Jang, Hsin-Hung Liao, Yeong-Jyh Lin, Hsiao-Chung Liang, Chung-Shi Liu
  • Patent number: 10504870
    Abstract: Embodiments of mechanisms for forming a package are provided. The package includes a substrate and a contact pad formed on the substrate. The package also includes a conductive pillar bonded to the contact pad through solder formed between the conductive pillar and the contact pad. The solder is in direct contact with the conductive pillar.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yeong-Jyh Lin, Hsin-Hung Liao, Chien Ling Hwang, Bor-Ping Jang, Hsiao-Chung Liang, Chung-Shi Liu
  • Publication number: 20190237422
    Abstract: The present disclosure, in some embodiments, relates to a semiconductor structure. The semiconductor structure includes a substrate and a first conductive pad arranged over the substrate. A boundary structure is on an upper surface of the substrate around the first conductive pad. The boundary structure has one or more sidewalls defining an opening with a round shape over the first conductive pad.
    Type: Application
    Filed: April 12, 2019
    Publication date: August 1, 2019
    Inventors: Chien Ling Hwang, Yeong-Jyh Lin, Bor-Ping Jang, Hsiao-Chung Liang
  • Publication number: 20190139949
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a first light-emitting diode (LED) layer including a first LED of a first color type, the first LED layer having a first side and a second side opposite to the first side; a second LED layer over the first LED layer, the second LED layer including a second LED of a second color type, and the second LED layer having a first side and a second side opposite to the first side; and a third LED layer over the second LED layer, the third LED layer including a third LED of a third color type, and the third LED layer having a first side and a second side opposite to the first side; wherein the first color type, the second color type, and the third color type are different from each other.
    Type: Application
    Filed: June 12, 2018
    Publication date: May 9, 2019
    Inventors: PING-YIN LIU, YEONG-JYH LIN, CHI-MING CHEN
  • Patent number: 10276531
    Abstract: The present disclosure relates to a semiconductor device. In some embodiments, the semiconductor device has a first plurality of conductive pads arranged over a first substrate. A conductive solder material is arranged over and is electrically connected to the first plurality of conductive pads. A first boundary structure separates each conductive pad of the first plurality of conductive pads from an adjacent conductive pad of the first plurality of conductive pads. A die is arranged over the first substrate. The die has outermost sidewalls that are laterally separated from first and second ones of the first plurality of conductive pads by the first boundary structure.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien Ling Hwang, Yeong-Jyh Lin, Bor-Ping Jang, Hsiao-Chung Liang
  • Publication number: 20190123018
    Abstract: A method includes placing a plurality of dummy dies over a carrier, placing a plurality of device dies over the carrier, molding the plurality of dummy dies and the plurality of device dies in a molding compound, forming redistribution line over and electrically coupled to the device dies, and performing a die-saw to separate the device dies and the molding compound into a plurality of packages.
    Type: Application
    Filed: December 17, 2018
    Publication date: April 25, 2019
    Inventors: Chien Ling Hwang, Bor-Ping Jang, Hsin-Hung Liao, Yeong-Jyh Lin, Hsiao-Chung Liang, Chung-Shi Liu
  • Patent number: 10157881
    Abstract: A method includes placing a plurality of dummy dies over a carrier, placing a plurality of device dies over the carrier, molding the plurality of dummy dies and the plurality of device dies in a molding compound, forming redistribution line over and electrically coupled to the device dies, and performing a die-saw to separate the device dies and the molding compound into a plurality of packages.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Bor-Ping Jang, Hsin-Hung Liao, Yeong-Jyh Lin, Hsiao-Chung Liang, Chung-Shi Liu
  • Publication number: 20180358255
    Abstract: A semiconductor device includes a carrier having a first central axis extending along a first direction and a second central axis extending along a second direction, a plurality of dies disposed on a surface of the carrier, and a plurality of scribing lines separating the plurality of dies from each other. The plurality of scribing lines include a plurality of continuous lines along the first direction and a plurality of discontinuous lines along the second direction, at least one of the plurality of continuous lines overlaps the first central axis, at least one of the plurality of discontinuous lines overlaps the second central axis. The plurality of dies are symmetrically arranged on the carrier about the first central axis and the second central axis.
    Type: Application
    Filed: August 20, 2018
    Publication date: December 13, 2018
    Inventors: BOR-PING JANG, CHIEN LING HWANG, HSIN-HUNG LIAO, YEONG-JYH LIN
  • Patent number: 10147693
    Abstract: An apparatus includes a spool configured to supply a wire, a cutting device configured to form a notch in the wire, and a capillary configured to bond the wire and to form a stud bump. The apparatus is further configured to pull the wire to break at the notch, with a tail region attached to the stud bump.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: December 4, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Yeong-Jyh Lin, Yi-Li Hsiao, Ming-Da Cheng, Tsai-Tsung Tsai, Chung-Shi Liu, Mirng-Ji Lii, Chen-Hua Yu
  • Patent number: 10056285
    Abstract: A method of dies singulation includes providing a carrier, disposing a plurality of dies over a surface of the carrier according to a plurality of scribe lines comprising a plurality of continuous lines along a first direction and a plurality of discontinuous lines along a second direction, cutting the carrier according to the plurality of continuous lines along the first direction, and cutting the carrier according to the plurality of discontinuous lines along the second direction.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: August 21, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Bor-Ping Jang, Chien Ling Hwang, Hsin-Hung Liao, Yeong-Jyh Lin
  • Publication number: 20180204816
    Abstract: A package includes first package component and a second package component. The first package component includes a first electrical connector at a surface of the first package component, and a first solder region on a surface of the first electrical connector. The second package component includes a second electrical connector at a surface of the second package component, and a second solder region on a surface of the second electrical connector. A metal pin has a first end bonded to the first solder region, and a second end bonded to the second solder region.
    Type: Application
    Filed: March 13, 2018
    Publication date: July 19, 2018
    Inventors: Chen-Hua Yu, Chien Ling Hwang, Yeong-Jyh Lin
  • Publication number: 20180175013
    Abstract: A mold includes a top portion, and an edge ring having a ring-shape. The edge ring is underlying and connected to edges of the top portion. The edge ring includes air vents. The edge ring further encircles the inner space under the top portion of the mold. A plurality of injection ports is connected to the inner space of the mold. The plurality of injection ports is substantially aligned to a straight line crossing a center of the top portion of the mold. The plurality of injection ports has different sizes.
    Type: Application
    Filed: February 12, 2018
    Publication date: June 21, 2018
    Inventors: Bor-Ping Jang, Chung-Shi Liu, Chien Ling Hwang, Yeong-Jyh Lin
  • Patent number: 9929118
    Abstract: A package includes first package component and a second package component. The first package component includes a first electrical connector at a surface of the first package component, and a first solder region on a surface of the first electrical connector. The second package component includes a second electrical connector at a surface of the second package component, and a second solder region on a surface of the second electrical connector. A metal pin has a first end bonded to the first solder region, and a second end bonded to the second solder region.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: March 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chien Ling Hwang, Yeong-Jyh Lin
  • Patent number: 9917069
    Abstract: A method of cleaning an apparatus for processing a semiconductor wafer includes providing a first device having a first surface configured to load a first semiconductor wafer, a second device having a second surface configured to load a second semiconductor wafer, and a first cleaning module; and cleaning the second surface by moving the first cleaning module across the second surface in a first direction with respect to the second device.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: March 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ping-Yin Liu, Yeong-Jyh Lin, Xin-Hua Huang, Chia-Shiung Tsai
  • Publication number: 20180043593
    Abstract: A method includes placing a package structure into a mold chase, with top surfaces of device dies in the package structure contacting a release film in the mold chase. A molding compound is injected into an inner space of the mold chase through an injection port, with the injection port on a side of the mold chase. During the injection of the molding compound, a venting step is performed through a first venting port and a second venting port of the mold chase. The first venting port has a first flow rate, and the second port has a second flow rate different from the first flow rate.
    Type: Application
    Filed: October 25, 2017
    Publication date: February 15, 2018
    Inventors: Bor-Ping Jang, Yeong-Jyh Lin, Chien Ling Hwang, Chung-Shi Liu, Meng-Tse Chen, Ming-Da Cheng, Chen-Hua Yu
  • Publication number: 20180047611
    Abstract: A method of dies singulation includes providing a carrier, disposing a plurality of dies over a surface of the carrier according to a plurality of scribe lines comprising a plurality of continuous lines along a first direction and a plurality of discontinuous lines along a second direction, cutting the carrier according to the plurality of continuous lines along the first direction, and cutting the carrier according to the plurality of discontinuous lines along the second direction.
    Type: Application
    Filed: October 23, 2017
    Publication date: February 15, 2018
    Inventors: BOR-PING JANG, CHIEN LING HWANG, HSIN-HUNG LIAO, YEONG-JYH LIN
  • Patent number: 9893044
    Abstract: A mold includes a top portion, and an edge ring having a ring-shape. The edge ring is underlying and connected to edges of the top portion. The edge ring includes air vents. The edge ring further encircles the inner space under the top portion of the mold. A plurality of injection ports is connected to the inner space of the mold. The plurality of injection ports is substantially aligned to a straight line crossing a center of the top portion of the mold. The plurality of injection ports has different sizes.
    Type: Grant
    Filed: January 19, 2015
    Date of Patent: February 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bor-Ping Jang, Chung-Shi Liu, Chien Ling Hwang, Yeong-Jyh Lin
  • Publication number: 20180005976
    Abstract: Embodiments of mechanisms for forming a package are provided. The package includes a substrate and a contact pad formed on the substrate. The package also includes a conductive pillar bonded to the contact pad through solder formed between the conductive pillar and the contact pad. The solder is in direct contact with the conductive pillar.
    Type: Application
    Filed: September 18, 2017
    Publication date: January 4, 2018
    Inventors: Yeong-Jyh Lin, Hsin-Hung Liao, Chien Ling Hwang, Bor-Ping Jang, Hsiao-Chung Liang, Chung-Shi Liu
  • Patent number: 9834435
    Abstract: Structures and formation methods of a semiconductor device structure are provided. A semiconductor device structure includes a semiconductor substrate including a cavity and a movable feature in the cavity. The semiconductor device structure also includes a cap substrate bonded to the semiconductor substrate to seal the cavity. There is an interface between the cap substrate and the semiconductor substrate. The semiconductor device structure further includes a sealing feature embedded in the semiconductor substrate and surrounding the cavity. The sealing feature extends across the interface and penetrates through the cap substrate.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: December 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ping-Yin Liu, Xin-Hua Huang, Yeong-Jyh Lin, Jung-Huei Peng