Patents by Inventor Yeong-Jyh T. Lii

Yeong-Jyh T. Lii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7176574
    Abstract: A conductive line varies in thickness to assist in overcoming RC delays and noise coupling. By varying line thickness, variation in conductor width is avoided if necessary to maintain a specified minimum pitch between conductors while maintaining predetermined desired RC parameters and noise characteristics of the conductive line. Conductor depth variation is achieved by etching a dielectric layer to different thicknesses. A subsequent conductive fill over the dielectric layer and in the differing thicknesses results in a conductive line that varies in thickness. Different conductive line thicknesses available at a particular metal level can additionally be used for semiconductor structures other than a signal or a power supply conductive line, such as a contact, a via or an electrode of a device. The thickness analysis required to determine how interconnect thickness is varied in order to meet a desired design criteria may be automated and provided as a CAD tool.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: February 13, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Kathleen C. Yu, Kirk J. Strozewski, Janos Farkas, Hector Sanchez, Yeong-Jyh T. Lii
  • Patent number: 6891229
    Abstract: A method of forming a semiconductor device so as to provide the device inverted isolation trenches with convex sidewalls. Initially, a plurality of composite isolation posts (50, 51) are formed on a substrate (40) through successive deposition, lithography, and etching steps. The posts comprise a bottom layer (501, 502) of silicon dioxide and an overlying etch-stop layer of silicon nitride (502, 512). An insulating material (60) is then deposited over the isolation posts and areas of the substrate. Isolation structures (70,71) are established by etching the insulating material to form convex sidewall spacers (701,702, 711, 712) at the vertical walls of the isolation posts. Active areas (80) between spacers are filled with semiconductor material. In an embodiment, a strained cap layer (101) may be imposed on the active areas. The strained cap layer has a lattice constant that is different from the lattice constant of the semiconductor material.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: May 10, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Andrea Franke, Jonathan Cobb, John M. Grant, Al T. Koh, Yeong-Jyh T. Lii, Bich-Yen Nguyen, Anna M. Phillips
  • Patent number: 6838354
    Abstract: Dummy features (64, 65, 48a, 48b) are formed within an interlevel dielectric layer (36). Passivation layers (32 and 54) are formed by electroless deposition to protect the underlying conductive regions (44, 48a, 48b and 30) from being penetrated from the air gaps (74). In addition, the passivation layers (32 and 54) overhang the underlying conductive regions (44, 48a, 48b and 30), thereby defining dummy features (65a, 65b and 67) adjacent the conductive regions (48a, 44 and 48b). The passivation layers (32 and 54) can be formed without additional patterning steps and help minimize misaligned vias from puncturing air gaps.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: January 4, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Cindy K. Goldberg, Stanley Michael Filipiak, John C. Flake, Yeong-Jyh T. Lii, Bradley P. Smith, Yuri E. Solomentsev, Terry G. Sparks, Kirk J. Strozewski, Kathleen C. Yu
  • Patent number: 6815820
    Abstract: A conductive line varies in thickness to assist in overcoming RC delays and noise coupling. By varying line thickness, variation in conductor width is avoided if necessary to maintain a specified minimum pitch between conductors while maintaining predetermined desired RC parameters and noise characteristics of the conductive line. Conductor depth variation is achieved by etching a dielectric layer to different thicknesses. A subsequent conductive fill over the dielectric layer and in the differing thicknesses results in a conductive line that varies in thickness. Different conductive line thicknesses available at a particular metal level can additionally be used for semiconductor structures other than a signal or a power supply conductive line, such as a contact, a via or an electrode of a device. The thickness analysis required to determine how interconnect thickness is varied in order to meet a desired design criteria may be automated and provided as a CAD tool.
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: November 9, 2004
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Kathleen C. Yu, Kirk J. Strozewski, Janos Farkas, Hector Sanchez, Yeong-Jyh T. Lii
  • Publication number: 20040217437
    Abstract: A method of forming a semiconductor device so as to provide the device inverted isolation trenches with convex sidewalls. Initially, a plurality of composite isolation posts (50, 51) are formed on a substrate (40) through successive deposition, lithography, and etching steps. The posts comprise a bottom layer (501, 502) of silicon dioxide and an overlying etch-stop layer of silicon nitride (502, 512). An insulating material (60) is then deposited over the isolation posts and areas of the substrate. Isolation structures (70,71) are established by etching the insulating material to form convex sidewall spacers (701,702, 711, 712) at the vertical walls of the isolation posts. Active areas (80) between spacers are filled with semiconductor material. In an embodiment, a strained cap layer (101) may be imposed on the active areas. The strained cap layer has a lattice constant that is different from the lattice constant of the semiconductor material.
    Type: Application
    Filed: April 30, 2003
    Publication date: November 4, 2004
    Inventors: Andrea Franke, Jonathan Cobb, John M. Grant, Al T. Koh, Yeong-Jyh T. Lii, Bich-Yen Nguyen, Anna M. Phillips
  • Patent number: 6774053
    Abstract: The present invention provides a low-k dielectric constant structure and method of forming the same on a substrate 10 that features having a dielectric layer 20 with differing regions of density 12 and 18. To that end, the method includes depositing, upon the substrate, a dielectric layer having first and second density regions. The density associated with the second density region being greater than the density associated with the first density region, and the first density region being disposed between the substrate and the second density region.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: August 10, 2004
    Assignees: Freescale Semiconductor, Inc., Advanced Micro Devices, Inc.
    Inventors: Errol Todd Ryan, Cindy K. Goldberg, Yuri Solomentsev, Yeong-Jyh T. Lii
  • Publication number: 20040119134
    Abstract: Dummy features (64, 65, 48a, 48b) are formed within an interlevel dielectric layer (36). Passivation layers (32 and 54) are formed by electroless deposition to protect the underlying conductive regions (44, 48a, 48b and 30) from being penetrated from the air gaps (74). In addition, the passivation layers (32 and 54) overhang the underlying conductive regions (44, 48a, 48b and 30), thereby defining dummy features (65a, 65b and 67) adjacent the conductive regions (48a, 44 and 48b). The passivation layers (32 and 54) can be formed without additional patterning steps and help minimize misaligned vias from puncturing air gaps.
    Type: Application
    Filed: December 20, 2002
    Publication date: June 24, 2004
    Inventors: Cindy K. Goldberg, Stanley Michael Filipiak, John C. Flake, Yeong-Jyh T. Lii, Bradley P. Smith, Yuri E. Solomentsev, Terry G. Sparks, Kirk J. Strozewski, Kathleen C. Yu
  • Patent number: 6689676
    Abstract: A method for providing gates of transistors with at least two different work functions utilizes a silicidation of two different metals at different times, silicidation for one gate and polysilicon for the other, or silicidation using a single metal with two differently doped silicon structures. Thus the problem associated with performing silicidation of two different metals at the same time is avoided. If the two metals have significantly different silicidation temperatures, the one with the lower temperature silicidation will likely have significantly degraded performance as a result of having to also experience the higher temperature required to achieve silicidation with the other metal.
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: February 10, 2004
    Assignee: Motorola, Inc.
    Inventors: Daniel Thanh-Khac Pham, Al T. Koh, Yeong-Jyh T. Lii, Robert F. Steimle, Anne Vandooren, Ricardo Garcia, Kimberly G. Reid, Marc Rossow, James P. Geren
  • Publication number: 20040018681
    Abstract: A method for providing gates of transistors with at least two different work functions utilizes a silicidation of two different metals at different times, silicidation for one gate and polysilicon for the other, or silicidation using a single metal with two differently doped silicon structures. Thus the problem associated with performing silicidation of two different metals at the same time is avoided. If the two metals have significantly different silicidation temperatures, the one with the lower temperature silicidation will likely have significantly degraded performance as a result of having to also experience the higher temperature required to achieve silicidation with the other metal.
    Type: Application
    Filed: July 26, 2002
    Publication date: January 29, 2004
    Inventors: Daniel Thanh-Khac Pham, Bich-Yen Nguyen, James K. Schaeffer, Melissa O. Zavala, Sherry G. Straub, Al T. Koh, Yeong-Jyh T. Lii, Robert F. Steimle, Anne Vandooren, Ricardo Garcia, Kimberly G. Reid, Marc Rossow, James P. Geren
  • Publication number: 20030209779
    Abstract: A conductive line varies in thickness to assist in overcoming RC delays and noise coupling. By varying line thickness, variation in conductor width is avoided if necessary to maintain a specified minimum pitch between conductors while maintaining predetermined desired RC parameters and noise characteristics of the conductive line. Conductor depth variation is achieved by etching a dielectric layer to different thicknesses. A subsequent conductive fill over the dielectric layer and in the differing thicknesses results in a conductive line that varies in thickness. Different conductive line thicknesses available at a particular metal level can additionally be used for semiconductor structures other than a signal or a power supply conductive line, such as a contact, a via or an electrode of a device. The thickness analysis required to determine how interconnect thickness is varied in order to meet a desired design criteria may be automated and provided as a CAD tool.
    Type: Application
    Filed: May 9, 2002
    Publication date: November 13, 2003
    Inventors: Kathleen C. Yu, Kirk J. Strozewski, Janos Farkas, Hector Sanchez, Yeong-Jyh T. Lii
  • Publication number: 20020171107
    Abstract: Epitaxial silicon is grown to form elevated source/drain extensions for transistors on silicon-on-insulator (SOI) substrates. An offset linear layer is formed between the gate and the epitaxial silicon to prevent shorting. In one embodiment, the offset linear layer is a nitride and in another embodiment it is an oxide. The resulting structure decreases extension resistance and improves the scalability of SOI transistors by increasing the thickness of silicon underneath the source and drain regions, while keeping the silicon underneath the gate thin. This allows for the reduction in gate length without decreasing the functionality of the transistor.
    Type: Application
    Filed: May 21, 2001
    Publication date: November 21, 2002
    Inventors: Baohong Cheng, Yeong-Jyh T. Lii
  • Patent number: 6369430
    Abstract: Insulating layers between transistors that are very close together may have voids. When contacts are formed in these areas between these close transistors, the contact hole is formed at the void location. These voids may extend between the contact locations that are close together so that the deposition of the conductive material into these contact holes may extend sufficiently into the void to short two such contacts. This is prevented by placing a liner in the contact hole, which constricts the void size in the contact hole, prior to depositing the conductive material. This restricts ingress of conductive material into the void. This prevents the void from being an unwanted conduction path between two contacts that are in close proximity. The bottoms of the contact holes are etched to remove the liner prior to depositing the conductive material.
    Type: Grant
    Filed: April 2, 2001
    Date of Patent: April 9, 2002
    Assignee: Motorola, Inc.
    Inventors: Olubunmi O. Adetutu, Yeong-Jyh T. Lii, Paul A. Grudowski
  • Patent number: 6362071
    Abstract: In accordance with one embodiment of the present invention, a method is disclosed for forming a semiconductor device having an isolation region (601). A dielectric layer (108) is deposited and etched to form isolation regions (102, 605) having top portions that are narrower than their bottom portions, thereby a tapered isolation region is formed. Active regions (601, 603) are formed using an epitaxial process in the regions between the isolation regions. The resulting active regions (601, 603) have a greater amount of surface area near a top portion, than near a bottom portion. Transistors (721, 723) having opposite polarities are formed within the active areas.
    Type: Grant
    Filed: April 5, 2000
    Date of Patent: March 26, 2002
    Assignee: Motorola, Inc.
    Inventors: Bich-Yen Nguyen, William J. Taylor, Jr., Philip J. Tobin, David L. O'Meara, Percy V. Gilbert, Yeong-Jyh T. Lii, Victor S. Wang
  • Patent number: 5378312
    Abstract: A method of fabricating a semiconductor structure includes the steps of providing a semiconductor substrate having a material disposed thereon, masking the material with a mask having an appropriate pattern for forming a semiconductor structure, etching unmasked portions of the material so as to form the semiconductor structure, wherein the etching produces a film which attaches onto the semiconductor structure and/or on the semiconductor substrate, and removing the film from the semiconductor structure according to the steps of producing a cryogenic jet stream having cryogenic particles therein, and directing the cryogenic jet stream at the film such that the crogenic jet stream impinges on and causes the film to decrease in temperature so that a high temperature gradient develops between the film and the semiconductor structure, the film detaching from the semiconductor structure and fracturing due to contraction caused by the decrease in temperature and high temperature gradient.
    Type: Grant
    Filed: December 7, 1993
    Date of Patent: January 3, 1995
    Assignee: International Business Machines Corporation
    Inventors: George G. Gifford, Yeong-Jyh T. Lii, Jin J. Wu