Patents by Inventor Yeun-Sang Park
Yeun-Sang Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10020273Abstract: According to aspects provided herein, a semiconductor device may include a bump providing improved reliability and reduced size. In some aspects, a conductive pad may be formed on a substrate, and a conductive support layer, which may be a pillar, may be formed on the conductive pad. An intermetallic compound (IMC) layer may be formed on the conductive support layer, and a solder layer may be formed on the IMC layer. In some aspects, the conductive support layer may be of a smaller width than the IMC layer. In some aspects, the conductive support layer may have side surfaces which are wider at the solder side than at the conductive pad side. In some aspects, other layers may be formed, such as a seed layer between the conductive pad and the conductive support layer, or a barrier layer between the conductive support layer and the IMC layer.Type: GrantFiled: November 8, 2016Date of Patent: July 10, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-il Choi, Hyoju Kim, Byunglyul Park, Yeun-Sang Park, Jubin Seo, Atsushi Fujisaki
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Patent number: 9728490Abstract: A semiconductor device includes a via structure penetrating through a substrate, a portion of the via structure being exposed over a surface of the substrate, a protection layer pattern structure provided on the surface of the substrate and including a first protection layer pattern and a second protection layer pattern, the first protection layer pattern surrounding a lower sidewall of the exposed portion of the via structure and exposing an upper sidewall of the exposed portion of the via structure, the second protection layer pattern exposing a portion of the top surface of the first protection layer pattern adjacent to the sidewall of the via structure, and a pad structure provided on the via structure and the protection layer pattern structure and covering the top surface of the first protection layer pattern exposed by the second protection layer pattern.Type: GrantFiled: May 10, 2016Date of Patent: August 8, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-Il Choi, Hyo-Ju Kim, Yeun-Sang Park, Atsushi Fujisaki, Kwang-Jin Moon, Byung-Lyul Park
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Patent number: 9679829Abstract: Provided are semiconductor devices and methods of fabricating the same. The device may include a substrate including a first surface and a second surface opposing each other, a through-silicon-via (TSV) electrode provided in a via hole that may be formed to penetrate the substrate, and an integrated circuit provided adjacent to the through electrode on the first surface. The through electrode includes a metal layer filling a portion of the via hole and an alloy layer filling a remaining portion of the via hole. The alloy layer contains at least two metallic elements, one of which may be the same as that contained in the metal layer, and the other of which may be different from that contained in the metal layer.Type: GrantFiled: July 24, 2015Date of Patent: June 13, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwangjin Moon, SungHee Kang, Taeseong Kim, Byung Lyul Park, Yeun-Sang Park, Sukchul Bang
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Publication number: 20170148753Abstract: According to aspects provided herein, a semiconductor device may include a bump providing improved reliability and reduced size. In some aspects, a conductive pad may be formed on a substrate, and a conductive support layer, which may be a pillar, may be formed on the conductive pad. An intermetallic compound (IMC) layer may be formed on the conductive support layer, and a solder layer may be formed on the IMC layer. In some aspects, the conductive support layer may be of a smaller width than the IMC layer. In some aspects, the conductive support layer may have side surfaces which are wider at the solder side than at the conductive pad side. In some aspects, other layers may be formed, such as a seed layer between the conductive pad and the conductive support layer, or a barrier layer between the conductive support layer and the IMC layer.Type: ApplicationFiled: November 8, 2016Publication date: May 25, 2017Inventors: Ju-il Choi, Hyoju KIM, Byunglyul PARK, Yeun-Sang PARK, Jubin SEO, Atsushi FUJISAKI
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Patent number: 9653623Abstract: In a method for fabricating a semiconductor, a first conductive pattern structure partially protruding upwardly from first insulating interlayer is formed in first insulating interlayer. A first bonding insulation layer pattern covering the protruding portion of first conductive pattern structure is formed on first insulating interlayer. A first adhesive pattern containing a polymer is formed on first bonding insulation layer pattern to fill a first recess formed on first bonding insulation layer pattern. A second bonding insulation layer pattern covering the protruding portion of second conductive pattern structure is formed on second insulating interlayer. A second adhesive pattern containing a polymer is formed on second bonding insulation layer pattern to fill a second recess formed on second bonding insulation layer pattern. The first and second adhesive patterns are melted. The first and second substrates are bonded with each other so that the conductive pattern structures contact each other.Type: GrantFiled: December 1, 2015Date of Patent: May 16, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yi-Koan Hong, Yeun-Sang Park, Byung-Lyul Park, Joo-Hee Jang
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Publication number: 20170110445Abstract: A semiconductor device having a chip stack and an interconnection terminal is provided. The chip stack includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on each other. The interconnection terminal is electrically coupled to the chip stack. The first semiconductor chip includes a first front surface and a first backside surface. The second semiconductor chip includes a second front surface, a second backside surface, a second circuit layer and a through-electrode which is electrically coupled to the second circuit layer and penetrates the second semiconductor chip. The third semiconductor chip includes a third front surface, a third backside surface opposite to the third front surface and a third circuit layer adjacent to the third front surface. The first front surface and the second front surface face each other. The third front surface and the second backside surface face each other.Type: ApplicationFiled: December 27, 2016Publication date: April 20, 2017Inventors: PIL-KYU KANG, Byung Lyul Park, Taeyeong Kim, Yeun-Sang Park, Dosun Lee, Ho-Jin Lee, Jinho Chun, JU-IL CHOI, Yi Koan Hong
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Publication number: 20170062308Abstract: A semiconductor device includes a via structure penetrating through a substrate, a portion of the via structure being exposed over a surface of the substrate, a protection layer pattern structure provided on the surface of the substrate and including a first protection layer pattern and a second protection layer pattern, the first protection layer pattern surrounding a lower sidewall of the exposed portion of the via structure and exposing an upper sidewall of the exposed portion of the via structure, the second protection layer pattern exposing a portion of the top surface of the first protection layer pattern adjacent to the sidewall of the via structure, and a pad structure provided on the via structure and the protection layer pattern structure and covering the top surface of the first protection layer pattern exposed by the second protection layer pattern.Type: ApplicationFiled: May 10, 2016Publication date: March 2, 2017Inventors: Ju-ll Choi, Hyo-Ju Kim, Yeun-Sang Park, Atsushi Fujisaki, Kwang-Jin Moon, Byung-Lyul Park
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Patent number: 9530706Abstract: A semiconductor device having a chip stack and an interconnection terminal is provided. The chip stack includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on each other. The interconnection terminal is electrically coupled to the chip stack. The first semiconductor chip includes a first front surface and a first backside surface. The second semiconductor chip includes a second front surface, a second backside surface, a second circuit layer and a through-electrode which is electrically coupled to the second circuit layer and penetrates the second semiconductor chip. The third semiconductor chip includes a third front surface, a third backside surface opposite to the third front surface and a third circuit layer adjacent to the third front surface. The first front surface and the second front surface face each other. The third front surface and the second backside surface face each other.Type: GrantFiled: March 26, 2015Date of Patent: December 27, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Pil-Kyu Kang, Byung Lyul Park, Taeyeong Kim, Yeun-Sang Park, Dosun Lee, Ho-Jin Lee, Jinho Chun, Ju-il Choi, Yi Koan Hong
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Publication number: 20160155862Abstract: In a method for fabricating a semiconductor, a first conductive pattern structure partially protruding upwardly from first insulating interlayer is formed in first insulating interlayer. A first bonding insulation layer pattern covering the protruding portion of first conductive pattern structure is formed on first insulating interlayer. A first adhesive pattern containing a polymer is formed on first bonding insulation layer pattern to fill a first recess formed on first bonding insulation layer pattern. A second bonding insulation layer pattern covering the protruding portion of second conductive pattern structure is formed on second insulating interlayer. A second adhesive pattern containing a polymer is formed on second bonding insulation layer pattern to fill a second recess formed on second bonding insulation layer pattern. The first and second adhesive patterns are melted. The first and second substrates are bonded with each other so that the conductive pattern structures contact each other.Type: ApplicationFiled: December 1, 2015Publication date: June 2, 2016Inventors: Yi-Koan HONG, Yeun-Sang PARK, Byung-Lyul PARK, Joo-Hee JANG
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Patent number: 9287251Abstract: In a method, a first opening is formed in a first insulating interlayer on a first substrate. A first conductive pattern structure contacting a first diffusion prevention insulation pattern and having a planarized top surface is formed in the first opening. Likewise, a second conductive pattern structure contacting a second diffusion prevention insulation pattern is formed in a second insulating interlayer on a second substrate. A plasma treatment process is performed on at least one of the first and second substrates having the first and second conductive pattern structures thereon, respectively. The first and second conductive pattern structures are contacted to each other to bond the first and second substrates.Type: GrantFiled: July 8, 2015Date of Patent: March 15, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Pil-Kyu Kang, Seok-Ho Kim, Tae-Yeong Kim, Hyo-Ju Kim, Byung-Lyul Park, Yeun-Sang Park, Jin-Ho An, Ho-Jin Lee, Joo-Hee Jang, Deok-Young Jung
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Publication number: 20160020197Abstract: In a method, a first opening is formed in a first insulating interlayer on a first substrate. A first conductive pattern structure contacting a first diffusion prevention insulation pattern and having a planarized top surface is formed in the first opening. Likewise, a second conductive pattern structure contacting a second diffusion prevention insulation pattern is formed in a second insulating interlayer on a second substrate, plasma treatment process is performed on at least one of the first and second substrates having the first and second conductive pattern structures thereon, respectively. The first and second conductive pattern structures are contacted to each other to bond the first and second substrates.Type: ApplicationFiled: July 8, 2015Publication date: January 21, 2016Inventors: Pil-Kyu Kang, Seok-Ho Kim, Tae-Yeong Kim, Hyo-Ju Kim, Byung-Lyul Park, Yeun-Sang Park, Jin-Ho An, Ho-Jin Lee, Joo-Hee Jang, Deok-Young Jung
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Publication number: 20150332967Abstract: Provided are semiconductor devices and methods of fabricating the same. The device may include a substrate including a first surface and a second surface opposing each other, a through-silicon-via (TSV) electrode provided in a via hole that may be formed to penetrate the substrate, and an integrated circuit provided adjacent to the through electrode on the first surface. The through electrode includes a metal layer filling a portion of the via hole and an alloy layer filling a remaining portion of the via hole. The alloy layer contains at least two metallic elements, one of which may be the same as that contained in the metal layer, and the other of which may be different from that contained in the metal layer.Type: ApplicationFiled: July 24, 2015Publication date: November 19, 2015Inventors: KWANGJIN MOON, SungHee KANG, TAESEONG KIM, Byung Lyul PARK, Yeun-Sang PARK, SUKCHUL BANG
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Patent number: 9153522Abstract: Provided are semiconductor devices and methods of fabricating the same. The device may include a substrate including a first surface and a second surface opposing each other, a through-silicon-via (TSV) electrode provided in a via hole that may be formed to penetrate the substrate, and an integrated circuit provided adjacent to the through electrode on the first surface. The through electrode includes a metal layer filling a portion of the via hole and an alloy layer filling a remaining portion of the via hole. The alloy layer contains at least two metallic elements, one of which may be the same as that contained in the metal layer, and the other of which may be different from that contained in the metal layer.Type: GrantFiled: September 16, 2013Date of Patent: October 6, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwangjin Moon, SungHee Kang, Taeseong Kim, Byung Lyul Park, Yeun-Sang Park, Sukchul Bang
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Publication number: 20150279825Abstract: A semiconductor device having a chip stack and an interconnection terminal is provided. The chip stack includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on each other. The interconnection terminal is electrically coupled to the chip stack. The first semiconductor chip includes a first front surface and a first backside surface. The second semiconductor chip includes a second front surface, a second backside surface, a second circuit layer and a through-electrode which is electrically coupled to the second circuit layer and penetrates the second semiconductor chip. The third semiconductor chip includes a third front surface, a third backside surface opposite to the third front surface and a third circuit layer adjacent to the third front surface. The first front surface and the second front surface face each other. The third front surface and the second backside surface face each other.Type: ApplicationFiled: March 26, 2015Publication date: October 1, 2015Inventors: Pil-Kyu KANG, Byung Lyul PARK, Taeyeong KIM, Yeun-Sang PARK, Dosun LEE, Ho-Jin LEE, Jinho CHUN, Ju-il CHOI, Yi Koan HONG
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Patent number: 8836142Abstract: Semiconductor devices are disclosed. The semiconductor device may include a semiconductor substrate having a first surface and a second surface opposite to each other and a pad trench formed at a portion of the second surface, a through-electrode penetrating the semiconductor substrate and protruding from a bottom surface of the pad trench. A buried pad may be disposed in the pad trench and may surround the through-electrode.Type: GrantFiled: June 6, 2013Date of Patent: September 16, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Yeun-Sang Park, Byung-Lyul Park, SungHee Kang, Taeseong Kim, Kwangjin Moon, Sukchul Bang
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Patent number: 8816499Abstract: Provided are electrical interconnections and methods for fabricating the same. The electrical interconnection may include a substrate including a bonding pad, a solder ball electrically connected to the bonding pad, a solder supporter on the bonding pad, a portion of the solder ball filling the solder supporter, and a metal layer between the bonding pad and the solder supporter, the metal layer having an ionization tendency lower than the bonding pad.Type: GrantFiled: March 14, 2013Date of Patent: August 26, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-il Choi, Jeong-Woo Park, Jeonggi Jin, Yeun-Sang Park
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Publication number: 20140084473Abstract: Provided are semiconductor devices and methods of fabricating the same. The device may include a substrate including a first surface and a second surface opposing each other, a through-silicon-via (TSV) electrode provided in a via hole that may be formed to penetrate the substrate, and an integrated circuit provided adjacent to the through electrode on the first surface. The through electrode includes a metal layer filling a portion of the via hole and an alloy layer filling a remaining portion of the via hole. The alloy layer contains at least two metallic elements, one of which may be the same as that contained in the metal layer, and the other of which may be different from that contained in the metal layer.Type: ApplicationFiled: September 16, 2013Publication date: March 27, 2014Inventors: KWANGJIN MOON, SungHee KANG, TAESEONG KIM, Byung Lyul PARK, Yeun-Sang PARK, SUKCHUL BANG
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Publication number: 20140008815Abstract: Semiconductor devices are disclosed. The semiconductor device may include a semiconductor substrate having a first surface and a second surface opposite to each other and a pad trench formed at a portion of the second surface, a through-electrode penetrating the semiconductor substrate and protruding from a bottom surface of the pad trench. A buried pad may be disposed in the pad trench and may surround the through-electrode.Type: ApplicationFiled: June 6, 2013Publication date: January 9, 2014Inventors: Yeun-Sang Park, Byung-Lyul Park, SungHee Kang, Taeseong Kim, Kwangjin Moon, Sukchul Bang
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Publication number: 20130313707Abstract: Provided are electrical interconnections and methods for fabricating the same. The electrical interconnection may include a substrate including a bonding pad, a solder ball electrically connected to the bonding pad, a solder supporter on the bonding pad, a portion of the solder ball filling the solder supporter, and a metal layer between the bonding pad and the solder supporter, the metal layer having an ionization tendency lower than the bonding pad.Type: ApplicationFiled: March 14, 2013Publication date: November 28, 2013Applicant: Samsung Electronics Co., Ltd.Inventors: Ju-il Choi, Jeong-woo Park, Jeonggi Jin, Yeun-Sang Park