Patents by Inventor Yi An SHIH
Yi An SHIH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11811114Abstract: The power supply device is configured on an aircraft and includes a secondary battery, a transformer, a fuel cell and a bypass switch. The transformer is electrically connected between the secondary battery and the aircraft. The fuel cell is suitable for providing a first output current to the aircraft. The bypass switch is connected in parallel with the transformer. The transformer has a first output voltage set value. When a first output terminal voltage of the fuel cell is lower than the first output voltage set value and the bypass switch is in a non-conducting state, a second output current of the secondary battery is provided to the aircraft via the transformer. When the first output terminal voltage is lower than the first output voltage set value and the bypass switch is in a conducting state, the second output current is provided to the aircraft via the bypass switch.Type: GrantFiled: December 30, 2020Date of Patent: November 7, 2023Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yin-Wen Tsai, Chih-Wei Hsu, Yuh-Fwu Chou, Chin-Yi Shih, Chien-Chi Chiu
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Patent number: 11812669Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, a top electrode layer on the magnetic tunnel junction stack, and a hard mask layer on said top electrode layer, wherein the material of top electrode layer is titanium nitride, a material of said hard mask layer is tantalum or tantalum nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.Type: GrantFiled: June 9, 2022Date of Patent: November 7, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, Jun Xie
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Publication number: 20230354556Abstract: A computing system including a water-resistant chassis, at least one electronic component with a heat sink, and a gap filler. The heat sink includes an arrangement of fins separated by inter-fin spaces. The gap filler is in contact with both the heat sink and the water-resistant chassis. The gap filler is positioned in the inter-fin spaces to provide a heat conduction path between the heat sink and the chassis.Type: ApplicationFiled: April 27, 2022Publication date: November 2, 2023Inventors: Yi-Chieh CHEN, Yueh-Chang WU, Ching-Yi SHIH, Kang HSU
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Publication number: 20230329003Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.Type: ApplicationFiled: June 13, 2023Publication date: October 12, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Da-Jun Lin, Yi-An Shih, Bin-Siang Tsai, Fu-Yu Tsai
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Publication number: 20230329004Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.Type: ApplicationFiled: June 14, 2023Publication date: October 12, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Da-Jun Lin, Yi-An Shih, Bin-Siang Tsai, Fu-Yu Tsai
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Publication number: 20230305716Abstract: A method for evaluating a margin of at least one parameter utilized by a transmission interface includes: step (A) setting a value of a first parameter utilized by a host device to a first test value selected from a first group; (B) setting a value of a second parameter utilized by a data storage device to a second test value selected from a second group; (C) controlling the data storage device to perform a predetermined testing procedure to test whether the data storage device functions normally when the first test value and the second test value are applied; and (D) changing the first test value or the second test value and re-performing steps (A) to (C), wherein step (D) is repeatedly performed until all the test values in the first group and the second group have been tested.Type: ApplicationFiled: December 5, 2022Publication date: September 28, 2023Applicant: Silicon Motion, Inc.Inventor: Po-Yi Shih
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Publication number: 20230309258Abstract: A dust-proof telecommunication system is disclosed. The dust-proof telecommunication system includes a chassis, critical components located within the chassis, and a filter module located within the chassis near at least some of the critical components that need to be cooled. For example, the critical components include a central processing unit (CPU), a system on chip (SoC), a memory module, a PCIe card, and/or a chipset. The filter module has a filter cover that surrounds at least in part the critical components, a first air filter located at an inlet of an airflow, and a second air filter located at an outlet. The critical components located at a protective space within the chassis receive and are cooled by the airflow passing through the air filter.Type: ApplicationFiled: March 22, 2022Publication date: September 28, 2023Inventors: Yi-Chieh CHEN, Yueh-Chang WU, Ching-Yi SHIH, Po-Cheng SHEN
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Patent number: 11765983Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.Type: GrantFiled: October 24, 2022Date of Patent: September 19, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chiu-Jung Chiu, Ya-Sheng Feng, I-Ming Tseng, Yi-An Shih, Yu-Chun Chen, Yi-Hui Lee, Chung-Liang Chu, Hsiu-Hao Hu
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Publication number: 20230262937Abstract: A heat sink comprises a first portion and a second portion. The first portion is configured to contact a heat-generating electronic component. The first portion is formed from a first group of materials and has a first plurality of fins. The second portion is coupled to the first portion. The second portion is formed from a second group of materials and has a second plurality of fins. The second group of materials is different than the first group of materials. The first group of materials can include extruded aluminum, stamped aluminum, or both. The second group of materials can include die-cast metal. The first plurality of fins can have a smaller fin pitch than the second plurality of fins. The heat sink can further comprise a third portion coupled to the first portion, such that the first portion is positioned between the second portion and the third portion.Type: ApplicationFiled: February 11, 2022Publication date: August 17, 2023Inventors: Yi-Chieh CHEN, Yueh-Chang WU, Ching-Yi SHIH, Kang HSU
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Patent number: 11723215Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.Type: GrantFiled: November 30, 2020Date of Patent: August 8, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Da-Jun Lin, Yi-An Shih, Bin-Siang Tsai, Fu-Yu Tsai
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Publication number: 20230238043Abstract: A semiconductor structure includes a substrate having a memory device region and a logic device region, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer on the memory device region, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and completely filling the spaces between the memory stack structures, and a first interconnecting structure formed in the second dielectric layer on the logic device region. A top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures.Type: ApplicationFiled: March 28, 2023Publication date: July 27, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Jing-Yin Jhang, Chien-Ting Lin
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Patent number: 11650942Abstract: The invention relates to a method, a non-transitory computer-readable storage medium, and an apparatus for executing an embedded multi-media card (eMMC) command. The method is performed by a processing unit of a flash controller to include: receiving an eMMC command from a host side; and performing a first function associated with a host performance acceleration (HPA) mode according to content of reserved bits of the eMMC command. The HPA mode allows the host side to allocate space in a system memory as an HPA buffer. The HPA buffer stores logical-block-address to physical-block-address (L2P) mapping entries obtained from the flash controller, and each L2P mapping entry stores information indicating which physical address that user data of a corresponding logical address is physically stored in a flash device, thereby enabling the host side to issue an HPA read command carrying the physical address to the flash controller.Type: GrantFiled: July 15, 2022Date of Patent: May 16, 2023Assignee: SILICON MOTION, INC.Inventor: Po-Yi Shih
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Patent number: 11646069Abstract: A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.Type: GrantFiled: August 30, 2021Date of Patent: May 9, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Jing-Yin Jhang, Chien-Ting Lin
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Publication number: 20230040932Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.Type: ApplicationFiled: October 24, 2022Publication date: February 9, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chiu-Jung Chiu, Ya-Sheng Feng, I-Ming Tseng, Yi-An Shih, Yu-Chun Chen, Yi-Hui Lee, Chung-Liang Chu, Hsiu-Hao Hu
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Publication number: 20230038528Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.Type: ApplicationFiled: October 18, 2022Publication date: February 9, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
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Patent number: 11568429Abstract: A demand forecasting method and a demand forecasting apparatus are provided. A preliminary prediction amount corresponding to a part number is obtained based on historical demand data. A demand probability of the part number is calculated based on the preliminary prediction amount. A prediction demand amount corresponding to the part number is obtained based on the historical demand data, the preliminary prediction amount and the demand probability.Type: GrantFiled: April 23, 2020Date of Patent: January 31, 2023Assignee: Wistron CorporationInventors: Chi Lin Tsai, Chi Hao Yu, Wen Hsuan Lan, Ling-Yu Kuo, Han-Yi Shih, Pei Yu Ho
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Patent number: 11552315Abstract: A control system and a control method of fuel cell stacks are provided. The control system includes a set of fuel cell stacks, a secondary battery, a monitoring device, and a control device. Each fuel cell stack has a power output that can be independently started up or shut down. The secondary battery is connected to power output terminals of the fuel cell stacks via a power transmission path. The monitoring device is configured to monitor an electrical parameter of the power transmission path. The control device receives an electrical parameter signal from the monitoring device, and outputs a control signal to shut down or start up the power output of at least one of the fuel cell stacks if the electrical parameter's value is higher than a predetermined upper limit or lower than a predetermined lower limit.Type: GrantFiled: April 14, 2021Date of Patent: January 10, 2023Assignee: Industrial Technology Research InstituteInventors: Yin-Wen Tsai, Chih-Wei Hsu, Ku-Yen Kang, Yuh-Fwu Chou, Chin-Yi Shih
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Publication number: 20230002778Abstract: Provided herein is a method for improving growth, stress tolerance and productivity of a plant. Also provided herein is a method for increasing seed quality of a plant. Specifically, the disclosure provides a method for improving growth, stress tolerance and productivity of a plant, comprising: providing a transgenic plant, which includes a reduced expression on an MYBS2 gene as relative to its wild-type counterpart; and a method for increasing seed quality of a plant, comprising: providing a seed from a transgenic plant, which overexpresses a full-length MYBS2 gene or a mutant MYBS2 gene as relative to its wild-type counterpart.Type: ApplicationFiled: September 17, 2020Publication date: January 5, 2023Applicants: ACADEMIA SINICA, NATIONAL CENTRAL UNIVERSITYInventors: Su-May YU, Yi-Shih CHEN, Chung-An LU, Tuan-Hua David HO
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Publication number: 20230005988Abstract: A semiconductor device includes a sense amplifier, a first magnetic tunneling junction (MTJ) connected to the sense amplifier at a first distance, a second MTJ connected to the sense amplifier at a second distance, and a third MTJ connected to the sense amplifier at a third distance. Preferably, the first distance is less than the second distance, the second distance is less than the third distance, a critical dimension of the first MTJ is less than a critical dimension of the second MTJ, and the critical dimension of the second MTJ is less than a critical dimension of the third MTJ.Type: ApplicationFiled: July 29, 2021Publication date: January 5, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Po-Wei Wang, Yi-An Shih, Huan-Chi Ma
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Patent number: 11544185Abstract: The invention relates to methods, and an apparatus for data reads in a host performance acceleration (HPA) mode. One method is performed by a host side to include: issuing a switch command to a flash controller to request the flash controller to activate an HPA function, and an acquisition function for a logical-block-address to physical-block-address (L2P) mapping table; issuing a write_multiple_block command to the flash controller to transfer a data block to a flash controller, where the data block includes a region number and a sub-region number; issuing a read_multiple_block command to the flash controller to obtain a plurality of L2P mapping entries corresponding to the region number and the sub-region number from the flash controller. The host side and the flash controller communicate with each other in an embedded multi-media card (eMMC) protocol.Type: GrantFiled: May 19, 2021Date of Patent: January 3, 2023Assignee: SILICON MOTION, INC.Inventor: Po-Yi Shih