Abstract: A driving mechanism includes a fixed part, a movable part, and a driving assembly. The movable part is movably connected to the fixed part for holding an optical element that has an optical axis. The driving assembly is configured to drive the movable part to move relative to the fixed part.

Abstract: A semiconductor structure and forming method thereof are provided. A substrate includes a first region, a second region, and a boundary region defined between the first region and the second region. An isolation structure is disposed in the boundary region. An upper surface of the isolation structure has a stepped profile. A first boundary dielectric layer and a second boundary dielectric layer are disposed over the isolation structure. The first boundary dielectric layer is substantially conformal with respect to the stepped profile of the isolation structure.

Abstract: An optical element driving mechanism is provided, including a movable portion, a fixed portion, and a driving assembly. The movable portion is connected to an optical element. The fixed portion includes a bottom. The movable portion is movable relative to the fixed portion. The driving assembly drives the movable portion to move relative to the fixed portion. The driving assembly drives the optical element to move relative to the fixed portion.

Abstract: The present disclosure relates to a force measuring device (1) comprising a spring module (2), and an electronic module (3), detachably mechanically connected to the spring module. The spring module comprises a test head (21) defining an outer surface of the device, a spring seat (23), and a spring (24) arranged between the test head and the spring seat, with a first end (24a) of the spring engaging the test head and a second end (24b) of the spring engaging the spring seat. The electronic module comprises a force sensor (31) arranged in physical contact with the spring seat.

Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.

Abstract: Ruthenium of a metal gate (MG) and/or a middle end of line (MEOL) structure is annealed to reduce, or even eliminate, seams after the ruthenium is deposited. Because the annealing reduces (or removes) seams in deposited ruthenium, electrical performance is increased because resistivity of the MG and/or the MEOL structure is decreased. Additionally, for MGs, the annealing generates a more even deposition profile, which results in a timed etching process producing a uniform gate height. As a result, more of the MGs will be functional after etching, which increases yield during production of the electronic device.

Abstract: A temperature measuring apparatus for measuring a temperature of a substrate is described. A light emitting source that emits light signals such as laser pulses are applied to the substrate. A detector on the other side of the light emitting source receives the reflected laser pulses. The detector further receives emission signals associated with temperature or energy density that is radiated from the surface of the substrate. The temperature measuring apparatus determines the temperature of the substrate during a thermal process using the received laser pulses and the emission signals. To improve the signal to noise ratio of the reflected laser pulses, a polarizer may be used to polarize the laser pulses to have a S polarization. The angle in which the polarized laser pulses are applied towards the substrate may also be controlled to enhance the signal to noise ratio at the detector's end.

Abstract: Some embodiments relate to an integrated chip structure. The integrated chip structure includes a substrate having a first device region and a second device region. A plurality of first transistor devices are disposed in the first device region and respectively include epitaxial source/drain regions disposed on opposing sides of a first gate structure. The epitaxial source/drain regions have an epitaxial material. A plurality of second transistor devices are disposed in the second device region and respectively include implanted source/drain regions disposed on opposing sides of a second gate structure. A dummy region includes one or more dummy structures. The one or more dummy structures have dummy epitaxial regions including the epitaxial material.

Abstract: An adjustment method of screen brightness comprises the following steps. Step (a): obtaining a relationship between a brightness and refresh rate of the screen. Step (b): adjusting the screen to a highest refresh rate and displaying an image at a first brightness. Step (c): decreasing the first brightness by a unit brightness value and variably displaying the image between a first refresh rate and a second refresh rate. Step (d): determining whether the image does not flicker; if not, repeating step (c). Step (e): calculating a first brightness difference between a decreased brightness of the screen and a brightness corresponding to a lowest refresh rate when the image does not flicker. Step (f): determining whether the first brightness difference is less than a screen flicker threshold; if yes, decreasing the first brightness corresponding to the highest refresh rate to obtain an adjusted brightness corresponding to the highest refresh rate.

Abstract: A cell region of a semiconductor device includes a first and second isolation dummy gates extending along a first direction. The semiconductor device further includes a first gate extending along the first direction and between the first isolation dummy gate and the second isolation dummy gate. The semiconductor device includes a second gate extending along the first direction, the second gate being between the first isolation dummy gate and the second isolation dummy gate relative to a second direction perpendicular to the first direction. The semiconductor device also includes a first active region and a second active region. The first active region extending in the second direction between the first isolation dummy gate and the second isolation dummy gate. The first active region has a first length in the second direction, and the second active region has a second length in the second direction different from the first length.

Abstract: A memory device includes active regions and gate structures, each of the gate structures is electrically coupled to a first portion of a corresponding active region of the active regions. The memory device includes contact-to-transistor-component structures (MD structures), each of the MD structures is over a second portion of a corresponding active region, and a first MD structure is between adjacent gate structures. The memory device includes via-to-gate/MD (VGD) structures, each of the VGD structures is over to a corresponding gate electrode and MD structure. The memory device includes conductive segments, each of the conductive segments is over and electrically coupled to a corresponding VGD structure. The memory device includes buried contact-to-transistor-component structures (BVD) structures, each of the BVD structures is under a third portion of a corresponding active region.

Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.

Abstract: The embodiments of the disclosure provide a patterning method, which includes the following processes. A target layer is formed on a substrate. A hard mask layer is formed over the target layer. A first patterning process is performed on the hard mask layer by using a photomask having a first pattern with a first pitch. The photomask is shifted along a first direction by a first distance. A second patterning process is performed on the hard mask layer by using the photomask that has been shifted, so as to form a patterned hard mask. The target layer is patterned using the patterned hard mask to form a patterned target layer. The target layer has a second pattern with a second pitch less than the first pitch.

Abstract: An optical component driving mechanism is provided. The optical component driving mechanism includes a first movable portion, a fixed portion, a first driving assembly, and a first support assembly. The first movable portion is configured to connect the first optical component. The first movable portion is movable relative to the fixed portion. The first driving assembly is configured to drive the first movable portion to move relative to the fixed portion. The first movable portion is movable relative to the fixed portion via the first support assembly. The first movable portion is movable relative to the fixed portion in a first dimension within a first-limit range.

Abstract: A projection lens module includes a projection lens and an adjustment device connected to the projection lens and adjusting a movement of the projection lens. The adjustment device includes a turntable, a combination plate, and an assembly member. The combination plate has an elastic member having a first combination unit. The assembly member includes a contact plate and a screw rod connecting the first surface of the contact plate. The second surface of the contact plate has a second combination unit clamped to the first combination unit. When the turntable rotates, the first combination unit drives the second combination unit to rotate around the axis. When the turntable maintains rotation and the assembly member is fixed, the elastic member generates elastic deformation, and therefore the first and second combination units are separated from each other so that the combination plate and the assembly member rotate relatively.

Abstract: A semiconductor device includes a substrate, a first gate, a plurality of second gates and a resistor. The substrate is defined with an active region and a resistor region. The first gate is disposed in the active region. The first gate has a first length extending along a first direction and a second length extending along a second direction. The plurality of second gates are disposed in the resistor region. Each of the second gates has a third length extending along the first direction and a fourth length extending along the second direction. The first length is equal to the third length, and the second length is equal to the fourth length. The resistor is disposed on the plurality of second gates.

Abstract: A voltage regulator for converting an input voltage to an output voltage includes: a first and a second high-side switch, a first and a second low-side switch and a control terminal which is for generating a reference voltage or determining a forced pass-through mode. The output voltage is determined according to the reference voltage during a buck mode and a boost mode. When the input voltage is higher than a first threshold, the voltage regulator is operated in the buck mode. When the input voltage is lower than a second threshold, the voltage regulator is operated in the boost mode. When the input voltage is lower than the first threshold and is higher than the second threshold, the voltage regulator is operated in a pass-through mode. When a voltage of the control terminal is lower than a third threshold, the voltage regulator is operated in the forced pass-through mode.

Abstract: A frame rate control method is provided. A primary scenario and a non-primary scenario are identified according to two or more windows displayed on a screen. Each of the primary scenario and the non-primary scenario is performed by an individual application. A frame rate of the non-primary scenario is decreased when a performance index indicates that a first condition is present. The application corresponding to the non-primary scenario is disabled when the performance index indicates that a second condition is present after decreasing the frame rate of the non-primary scenario, so as to remove the window corresponding to the non-primary scenario from the screen.

Abstract: A light-emitting device is provided. The light-emitting device generates a white light and includes at least one light-emitting diode. The at least one light-emitting diode generates a light beam with a broadband blue spectrum and includes a first semiconductor layer, a second semiconductor layer and a multiple quantum well structure. The multiple quantum well structure is located between the first semiconductor layer and the second semiconductor layer, and includes well layers and barrier layers. The well layers include a first well layer, a second well layer and third well layers different in indium concentrations. The first well layer has the largest indium concentration, and the third well layers have the smallest indium concentration. Three of the well layers that are closest to the first semiconductor layer are the third well layers, and the first well layer is closer to the second semiconductor layer than the first semiconductor layer.

Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.