Abstract: A method for compressing an image frame. Display data of a plurality of image blocks in the image frame is transmitted in a raster san order to a post-processing circuit. Upon receiving the display data of one image block, the post-processing circuit reads intermediate data of a buffering image block corresponding to the image block from a buffer memory, performs post-processing on the intermediate data of the buffering image block and display data of a main sub-block in the image block according to the display data of the image block and the intermediate data of the buffering image block to generate post-processed data of a post-processed image block, and stores the intermediate data of an intermediate image block in the image block to the buffer memory. A compressor compresses the post-processed data of the post-processed image block into compression data of the post-processed image block.

Abstract: A method for compressing image data is provided. The image data includes a file to be compressed, which includes N blocks to be compressed. The method includes: setting a target data increment of each of the N blocks of the file according to a 0th accumulated target data size and an Nth accumulated target data size; before compressing an nth block, calculating an (n?1)th accumulated target data size of an (n?1)th block according to the 0th accumulated target data size and the target data increment; when a difference between an (n?1)th accumulated compressed data size and the (n?1)th accumulated target data size is smaller than a predetermined threshold, removing X least significant bit(s) of a plurality of sets of data in the nth block to generate an updated nth block; and compressing the updated nth block to generate a compressed nth block.

Abstract: A method for compressing image data is provided. The image data includes a file to be compressed, which includes N blocks to be compressed. The method includes: setting a target data increment of each of the N blocks of the file according to a 0th accumulated target data size and an Nth accumulated target data size; before compressing an nth block, calculating an (n?1)th accumulated target data size of an (n?1)th block according to the 0th accumulated target data size and the target data increment; when a difference between an (n?1)th accumulated compressed data size and the (n?1)th accumulated target data size is smaller than a predetermined threshold, removing X least significant bit(s) of a plurality of sets of data in the nth block to generate an updated nth block; and compressing the updated nth block to generate a compressed nth block.

Abstract: A video stream decoding system includes a video decoder, a frame encoder and a buffer. The frame encoder includes a prediction unit and a compressor. The prediction unit predicts an image data group in a prediction block of a frame to generate a predicted image data group. The prediction image data group includes a first sub predicted image data group and a second sub predicted image data group. The compressor compresses the first sub predicted image data group in a unit of the first sub predicted image data group to generate a first compressed image data group, and compresses the second sub predicted image data group in a unit of the second sub predicted image data group to generate a second compressed data image group.

Abstract: A video stream decoding system includes a video decoder, a frame encoder, a buffer and a frame decoder. The video decoder receives a video stream, and decodes an encoded frame in the video stream to generate a frame. The frame includes a plurality of coding blocks. The frame encoder includes a first compressor, a second compressor and a selector. The first compressor compresses an image data group in a coding block according to a first compression algorithm to generate a first compressed image data group. The second compressor compresses the image data group in the coding block according to a second compression algorithm to generate a second compressed image data group. The first compression algorithm is different from the second compression algorithm.

Abstract: A method for controlling an electronic device is provided. The method includes detecting a first tilt angle between the electronic device and a reference plane, and controlling the electronic device to perform an operating according to the first tilt angle. The operation is associated with a user interface operation or an audio/video playback operation.

Abstract: A signal transceiver includes a connector for receiving a signal, a band-pass filter coupled to the connector for filtering the signal, a front-end module for demodulating the signal and an adaptive impedance switch circuit coupled between the band-pass filter and the front-end module for switching an impedance value between the band-pass filter and the front-end module.

Abstract: A quantized coefficient coding apparatus used in a media coding system includes a determination module, a coding mode arbitration module and a coding module. The determination module determines whether a set of quantized coefficients are defined in a predetermined variable length coding (VLC) table to generate a determination result. When the determination result of the determination module is negative, the coding mode arbitration module determines a best coding mode corresponding to the set of quantized coefficients from a plurality of predetermined coding modes. The coding mode encodes the set of quantized coefficients according to the best coding mode.

Abstract: A method for controlling an electronic device is provided. The method includes detecting a first tilt angle between the electronic device and a reference plane, and controlling the electronic device to perform an operating according to the first tilt angle. The operation is associated with a user interface operation or an audio/video playback operation.

Abstract: A signal transceiver includes a connector for receiving a signal, a band-pass filter coupled to the connector for filtering the signal, a front-end module for demodulating the signal and an adaptive impedance switch circuit coupled between the band-pass filter and the front-end module for switching an impedance value between the band-pass filter and the front-end module.

Abstract: An image processing apparatus including a processor and a memory is provided. The processor generates a target frame according to a reference frame stored in a storage region. The target frame has a first image data amount, and the reference frame has a second image data amount. The memory includes the storage region for storing the reference image and the target image. The processor has the target frame selectively overwrite a part of the reference frame. The capacity of the storage region is smaller than a sum of the first image data amount and the second image data amount, and is greater than the second image data amount.

Abstract: An electronic device is provided. The electronic device includes a substrate and a joint. The substrate includes a first surface and a second surface, wherein a substrate signal contact, two ground contacts and two positioning openings are formed on the substrate, and the positioning openings are respectively formed on the ground contact and pass through the substrate. The joint includes a connection port, a joint signal contact and two ground structure, wherein the connection port is electrically connected to the joint signal contact, the joint signal contact is connected to the substrate signal contact, and the joint signal contact is located between the two ground structures, and the ground structures are respectively inserted into the positioning openings to be electrically connected to the ground contacts.

Abstract: An electronic device is provided. The electronic device includes a substrate and a joint. The substrate includes a first surface and a second surface, wherein a substrate signal contact, two ground contacts and two positioning openings are formed on the substrate, and the positioning openings are respectively formed on the ground contact and pass through the substrate. The joint includes a connection port, a joint signal contact and two ground structure, wherein the connection port is electrically connected to the joint signal contact, the joint signal contact is connected to the substrate signal contact, and the joint signal contact is located between the two ground structures, and the ground structures are respectively inserted into the positioning openings to be electrically connected to the ground contacts.

Abstract: A quantized coefficient coding apparatus used in a media coding system includes a determination module, a coding mode arbitration module and a coding module. The determination module determines whether a set of quantized coefficients are defined in a predetermined variable length coding (VLC) table to generate a determination result. When the determination result of the determination module is negative, the coding mode arbitration module determines a best coding mode corresponding to the set of quantized coefficients from a plurality of predetermined coding modes. The coding mode encodes the set of quantized coefficients according to the best coding mode.

Abstract: A decoder for decoding a message using an arbitrary-side growing (ASG) Huffman tree including a plurality of codewords and symbols includes a database, a processing module, and a bit pattern matching module. The database stores a plurality of parameters corresponding to the ASG Huffman tree divided into several sub-trees according to a Hashemian cut operation and a bits-pattern-Xor (BPX) operation. The plurality of parameters include a bit pattern of a sub-tree of the ASG Huffman tree divided according to the BPX operation and a code length of the bit pattern. The processing module receives a bit stream corresponding to the ASG Huffman tree from an encoder. The bit pattern matching module selects bits from the bit stream according to the code length of the bit pattern and decodes the selected bits into a symbol in the ASG Huffman tree by comparing the selected bits with the bit pattern.

Abstract: A decoder for decoding a message using an arbitrary-side growing (ASG) Huffman tree including a plurality of codewords and symbols includes a database, a processing module, and a bit pattern matching module. The database stores a plurality of parameters corresponding to the ASG Huffman tree divided into several sub-trees according to a Hashemian cut operation and a bits-pattern-Xor (BPX) operation. The plurality of parameters include a bit pattern of a sub-tree of the ASG Huffman tree divided according to the BPX operation and a code length of the bit pattern. The processing module receives a bit stream corresponding to the ASG Huffman tree from an encoder. The bit pattern matching module selects bits from the bit stream according to the code length of the bit pattern and decodes the selected bits into a symbol in the ASG Huffman tree by comparing the selected bits with the bit pattern.

Abstract: The conventional I/O devices of a storage element, such as memory card, have a built-in microprocessor control unit (MCU) for executing the I/O commands. The demand of MCU increases the cost. Besides, the capacity of the storage element supported by the device is depend on the firmware inside the MCU. Since the updating of firmware is a tough job, the supportability is lack of elasticity. This invention discloses a method for driving the I/O device of storage element that strengthens the device driver to get rid of the MCU. The capacity supported hence can be raised by merely updating the device driver.

Abstract: The conventional apparatus for reading/writing storage devices need a built-in microprocessor control unit (MCU) to process commands. Thus, the flexiability (e.g.: supporting capacity of storage device) and the cost of the apparatus are not satisfied. The present invention employs a driver and a hardwire circuit to replace the MCU for money saving without changing other units in the apparatus. Moreover, the apparatus of the present invention can raise the supporting capacity of storage device and compatibility by just updating the driver.