Patents by Inventor Yi-Chuan Lo

Yi-Chuan Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230377881
    Abstract: Strain relief trenches may be formed in a substrate prior to growth of an epitaxial layer on the substrate. The trenches may reduce the stresses and strains on the epitaxial layer that occur during the epitaxial growth process due to differences in material properties (e.g., lattice mismatches, differences in thermal expansion coefficients, and/or the like) between the epitaxial layer material and the substrate material. The stress and strain relief provided by the trenches may reduce or eliminate cracks and/or other types of defects in the epitaxial layer and the substrate, may reduce and/or eliminate bowing and warping of the substrate, may reduce breakage of the substrate, and/or the like. This may increase the center-to-edge quality of the epitaxial layer, may permit epitaxial layers to be grown on larger substrates, and/or the like.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Inventors: Yi-Chuan LO, Pravanshu MOHANTA, Jiang-He XIE, Ching Yu CHEN, Ming-Tsung CHEN, Chia-Ling YEH
  • Patent number: 11804374
    Abstract: Strain relief trenches may be formed in a substrate prior to growth of an epitaxial layer on the substrate. The trenches may reduce the stresses and strains on the epitaxial layer that occur during the epitaxial growth process due to differences in material properties (e.g., lattice mismatches, differences in thermal expansion coefficients, and/or the like) between the epitaxial layer material and the substrate material. The stress and strain relief provided by the trenches may reduce or eliminate cracks and/or other types of defects in the epitaxial layer and the substrate, may reduce and/or eliminate bowing and warping of the substrate, may reduce breakage of the substrate, and/or the like. This may increase the center-to-edge quality of the epitaxial layer, may permit epitaxial layers to be grown on larger substrates, and/or the like.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: October 31, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chuan Lo, Pravanshu Mohanta, Jiang-He Xie, Ching Yu Chen, Ming-Tsung Chen, Chia-Ling Yeh
  • Publication number: 20220130670
    Abstract: Strain relief trenches may be formed in a substrate prior to growth of an epitaxial layer on the substrate. The trenches may reduce the stresses and strains on the epitaxial layer that occur during the epitaxial growth process due to differences in material properties (e.g., lattice mismatches, differences in thermal expansion coefficients, and/or the like) between the epitaxial layer material and the substrate material. The stress and strain relief provided by the trenches may reduce or eliminate cracks and/or other types of defects in the epitaxial layer and the substrate, may reduce and/or eliminate bowing and warping of the substrate, may reduce breakage of the substrate, and/or the like. This may increase the center-to-edge quality of the epitaxial layer, may permit epitaxial layers to be grown on larger substrates, and/or the like.
    Type: Application
    Filed: October 27, 2020
    Publication date: April 28, 2022
    Inventors: Yi-Chuan LO, Pravanshu MOHANTA, Jiang-He XIE, Ching Yu CHEN, Ming-Tsung CHEN, Chia-Ling YEH
  • Patent number: 11085849
    Abstract: An optical test method is provided. The optical test method includes emitting light through a gap between two substrates of a tested optical element disposed on a holder to generate a plurality of light beams. The optical test method further includes driving the holder with the tested optical element to move to N positions. The optical test method also includes receiving one of the light beams from the tested optical element in the N positions to generate N first intensity signals. In addition, the optical test method includes determining the size of the gap of the tested optical element according to the N first intensity signals and reference data.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Clark Lee, Yi-Chuan Lo, Hsun-Peng Lin, Chih-Ming Hong
  • Patent number: 10649336
    Abstract: A system for fabricating a semiconductor device includes a first supplier, a second supplier, a mixer, and an applier. The first supplier is configured to supply a developer solution having a first chemical. The second supplier is configured to supply the second chemical to the mixer. The mixer is configured to mix the developer solution with a second chemical, in which the second chemical is configured to form a plurality of bubbles in the developer solution. The applier is configured to apply the developer solution mixed with the bubbles onto a photoresist layer formed on a substrate, in which the photoresist layer has an exposed region, and the first chemical is configured to dissolve the exposed region of the photoresist layer through a chemical reaction.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: May 12, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jun-Yih Yu, Chang-Fa Lin, Ching-Hung Cheng, Yi-Chuan Lo, Ming-Hsuan Chuang
  • Publication number: 20200116588
    Abstract: An optical test method is provided. The optical test method includes emitting light through a gap between two substrates of a tested optical element disposed on a holder to generate a plurality of light beams. The optical test method further includes driving the holder with the tested optical element to move to N positions. The optical test method also includes receiving one of the light beams from the tested optical element in the N positions to generate N first intensity signals. In addition, the optical test method includes determining the size of the gap of the tested optical element according to the N first intensity signals and reference data.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventors: Clark LEE, Yi-Chuan LO, Hsun-Peng LIN, Chih-Ming HONG
  • Patent number: 10508971
    Abstract: An optical test method is provided. The optical test method includes emitting light through a gap between two substrates of a tested optical element disposed on a holder to generate a plurality of light beams. The optical test method further includes driving the holder with the tested optical element to move to N positions. The optical test method also includes receiving one of the light beams from the tested optical element in the N positions to generate N first intensity signals. In addition, the optical test method includes determining the size of the gap of the tested optical element according to the N first intensity signals and reference data.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Clark Lee, Yi-Chuan Lo, Hsun-Peng Lin, Chih-Ming Hong
  • Publication number: 20190072454
    Abstract: An optical test method is provided. The optical test method includes emitting light through a gap between two substrates of a tested optical element disposed on a holder to generate a plurality of light beams. The optical test method further includes driving the holder with the tested optical element to move to N positions. The optical test method also includes receiving one of the light beams from the tested optical element in the N positions to generate N first intensity signals. In addition, the optical test method includes determining the size of the gap of the tested optical element according to the N first intensity signals and reference data.
    Type: Application
    Filed: June 28, 2018
    Publication date: March 7, 2019
    Inventors: Clark LEE, Yi-Chuan LO, Hsun-Peng LIN, Chih-Ming HONG
  • Publication number: 20170092497
    Abstract: A system for fabricating a semiconductor device includes a first supplier, a second supplier, a mixer, and an applier. The first supplier is configured to supply a developer solution having a first chemical. The second supplier is configured to supply the second chemical to the mixer. The mixer is configured to mix the developer solution with a second chemical, in which the second chemical is configured to form a plurality of bubbles in the developer solution. The applier is configured to apply the developer solution mixed with the bubbles onto a photoresist layer formed on a substrate, in which the photoresist layer has an exposed region, and the first chemical is configured to dissolve the exposed region of the photoresist layer through a chemical reaction.
    Type: Application
    Filed: September 30, 2015
    Publication date: March 30, 2017
    Inventors: Jun-Yih YU, Chang-Fa LIN, Ching-Hung CHENG, Yi-Chuan LO, Ming-Hsuan CHUANG
  • Patent number: 9117714
    Abstract: An exemplary wafer level package comprises a semiconductor wafer with a plurality of semiconductor chips of perfect polygonal shapes thereon. A circuit-free area is defined over the semiconductor wafer to electrically isolate the semiconductor chips. A dam structure is substantially formed over the circuit-free area, wherein a portion of the dam structure formed around an edge of the semiconductor wafer is formed with a plurality via holes therein. A transparent substrate is formed over the semiconductor wafer, defining a plurality of cavities between the semiconductor chips and the transparent substrate, wherein the transparent substrate is supported by the dam structure.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: August 25, 2015
    Assignee: VisEra TECHNOLOGIES COMPANY LIMITED
    Inventors: Fu-Tien Weng, Yung-Shun Liao, Yi-Chuan Lo, Bii-Cheng Chang
  • Patent number: 8361830
    Abstract: An image sensor module having a light gathering region and a light non-gathering region includes an image sensor, a light blocking spacer, a lens layer and a fixing shell. The light blocking spacer is disposed on the image sensor and located in the light non-gathering region. The light blocking spacer has a through hole exposing a portion of the image sensor in the light gathering region. The lens layer is disposed on the light blocking spacer and covers the through hole. The lens layer includes a transparent substrate and a lens disposed on the transparent substrate and located in the light gathering region. The fixing shell located in the light non-gathering region wraps the sidewalls of the image sensor, the light blocking spacer and the lens layer continuously. The material of the fixing shell includes a thermosetting material. A method for manufacturing the image sensor module is also provided.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: January 29, 2013
    Assignee: Himax Semiconductor, Inc.
    Inventors: Chuan-Hui Yang, Hsin-Chang Hsiung, Yi-Chuan Lo, Han-Yi Kuo
  • Publication number: 20110248367
    Abstract: An image sensor module having a light gathering region and a light non-gathering region includes an image sensor, a light blocking spacer, a lens layer and a fixing shell. The light blocking spacer is disposed on the image sensor and located in the light non-gathering region. The light blocking spacer has a through hole exposing a portion of the image sensor in the light gathering region. The lens layer is disposed on the light blocking spacer and covers the through hole. The lens layer includes a transparent substrate and a lens disposed on the transparent substrate and located in the light gathering region. The fixing shell located in the light non-gathering region wraps the sidewalls of the image sensor, the light blocking spacer and the lens layer continuously. The material of the fixing shell includes a thermosetting material. A method for manufacturing the image sensor module is also provided.
    Type: Application
    Filed: April 9, 2010
    Publication date: October 13, 2011
    Applicant: HIMAX SEMICONDUCTOR, INC.
    Inventors: Chuan-Hui Yang, Hsin-Chang Hsiung, Yi-Chuan Lo, Han-Yi Kuo
  • Patent number: 7687211
    Abstract: A method for photolithography in semiconductor device manufacturing comprises defining test critical dimension target for a photolithography mask, measuring a mask critical dimension, comparing mask critical dimension to the test critical dimension target and determining a critical dimension deviation, determining a photolithography light base energy in response to the critical dimension deviation, and exposing the wafer according to the photolithography light base energy.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: March 30, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shui-Tien Lin, Shin-Rung Lu, Yi-Chuan Lo
  • Publication number: 20090102005
    Abstract: An exemplary wafer level package comprises a semiconductor wafer with a plurality of semiconductor chips of perfect polygonal shapes thereon. A circuit-free area is defined over the semiconductor wafer to electrically isolate the semiconductor chips. A dam structure is substantially formed over the circuit-free area, wherein a portion of the dam structure formed around an edge of the semiconductor wafer is formed with a plurality via holes therein. A transparent substrate is formed over the semiconductor wafer, defining a plurality of cavities between the semiconductor chips and the transparent substrate, wherein the transparent substrate is supported by the dam structure.
    Type: Application
    Filed: October 19, 2007
    Publication date: April 23, 2009
    Inventors: Fu-Tien Weng, Yung-Shun Liao, Yi-Chuan Lo, Bii-Cheng Chang
  • Patent number: 7385596
    Abstract: In a stylus attachment structure for an IT product, the attachment structure formed on an IT product, such as, a laptop, a tablet PC and a PDA, comprises an attachment slot, a push-out member, a retaining member and an elastic part, wherein the push-out member is arranged in the attachment slot and the retaining member is slidably mounted at one end of the attachment slot for selectively retaining or releasing the stylus. In this way, when the stylus is not in use for a while, it can be obliquely plugged to one end of the attachment slot, it is easy for the user to pick up the stylus; alternatively, the stylus can be fully received in the attachment socket and further secured in place with a retaining member, thereby enabling the stylus to be attached properly so that it doesn't become loose.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: June 10, 2008
    Assignee: First International Computer Inc.
    Inventors: Shui-Yuan Lin, Yi-Chuan Lo, Chih-Kuang Chiang
  • Publication number: 20060228865
    Abstract: A method for photolithography in semiconductor device manufacturing comprises defining test critical dimension target for a photolithography mask, measuring a mask critical dimension, comparing mask critical dimension to the test critical dimension target and determining a critical dimension deviation, determining a photolithography light base energy in response to the critical dimension deviation, and exposing the wafer according to the photolithography light base energy.
    Type: Application
    Filed: July 29, 2005
    Publication date: October 12, 2006
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shui-Tien Lin, Shin-Rung Lu, Yi-Chuan Lo
  • Publication number: 20060133015
    Abstract: In a stylus attachment structure for an IT product, the attachment structure formed on an IT product, such as, a laptop, a tablet PC and a PDA, comprises an attachment slot, a push-out member, a retaining member and an elastic part, wherein the push-out member is arranged in the attachment slot and the retaining member is slidably mounted at one end of the attachment slot for selectively retaining or releasing the stylus. In this way, when the stylus is not in use for a while, it can be obliquely plugged to one end of the attachment slot, it is easy for the user to pick up the stylus; alternatively, the stylus can be fully received in the attachment socket and further secured in place with a retaining member, thereby enabling the stylus to be attached properly so that it doesn't become loose.
    Type: Application
    Filed: December 17, 2004
    Publication date: June 22, 2006
    Inventors: Shui-Yuan Lin, Yi-Chuan Lo, Chih-Kuang Chiang
  • Patent number: 6898471
    Abstract: A multiple run by run process is described. A plurality of tools and a plurality of products to be run on the tools are provided. A desired recipe is calculated for each product on each tool based on a previous recipe used for each product on each tool and deviation of a parameter from a target value. Thereafter, the plurality of products is run on the plurality of tools. The desired recipe is updated after each run of each tool.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: May 24, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Cheng-I Sun, Yu Pen Fun, Yi-Chuan Lo, Wei-Hsuang Huang, Hsiang-Ming Lin
  • Patent number: 6893882
    Abstract: A multiple run by run process is described. A plurality of tools and a plurality of products to be run on the tools are provided. Tool effects and product effects on a parameter are identified for each tool and each product. A desired recipe is calculated for each product on each tool based on the tool effects and product effects identified. Thereafter, the plurality of products is run on the plurality of tools. The desired recipe is updated after each run of each tool. Tool aging is calculated after each run of each tool based on the desired recipe used.
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: May 17, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-I Sun, Ben Fung, Yi-Chuan Lo, Wei-Hsuang Huang, Hsiang-Min Lin
  • Patent number: 6865438
    Abstract: An advanced process control method using time interval between lots of a particular product to control the weighting of feedback data is described. A plurality of products are fabricated wherein the products are tracked by the process control method based on product type, for example. Variation in a parameter is detected. The adjustment speed of a process recipe is determined based on a time interval weighting wherein the time interval is defined as the time between processing of lots of the same product type. The process recipe is updated at the determined adjustment speed to decrease variation of the parameter.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: March 8, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shui-Tien Lin, Yi-Chuan Lo, Jimmy Hu, Chen-Yu Chang