Patents by Inventor YI-CHUN KAO

YI-CHUN KAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10978498
    Abstract: An array substrate includes a substrate, a first TFT, a second TFT, and a third TFT. The first TFT includes a first channel layer on the substrate, a first gate insulator layer, a first gate electrode, a first dielectric layer, and a second dielectric layer. The second TFT includes a first semiconductor layer on the substrate, a second gate insulator layer, a second gate electrode, a third dielectric layer, and a second channel layer. The first channel layer is made of a semiconducting material containing polycrystalline silicon. The second channel layer is made of a semiconducting material containing metal oxide. The first dielectric layer is made of silicon nitride; the second dielectric layer and the third dielectric layer are made of silicon oxide.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: April 13, 2021
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Hsin-Hua Lin, Yi-Chun Kao
  • Patent number: 10749039
    Abstract: A high-performance TFT substrate (100) for a flat panel display includes a substrate (110), a first conductive layer (130) on the substrate (110), a semiconductor layer (103) positioned on the first conductive layer (130), and a second conductive layer (150) positioned on the semiconductor layer (103). The first conductive layer (130) defines a gate electrode (101). The second conductive layer (150) defines a source electrode (105) and a drain electrode (106) spaced apart from the source electrode (105). The second conductive layer (150) includes a first layer (151) on the semiconductor layer (103) and a second layer (152) positioned on the first layer (151). The first layer (151) can be made of metal oxide. The second layer (152) can be made of aluminum or aluminum alloy.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: August 18, 2020
    Assignees: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yi-Chun Kao, Po-Li Shih, Wei-Chih Chang, I-Wei Wu
  • Patent number: 10727309
    Abstract: A thin film transistor array panel includes a first conductive layer (102) including a gate electrode; a channel layer (104) disposed over the gate; and a second conductive layer (105) disposed over the channel layer (104). The second conductive layer (105) includes a multi-layered portion defining a source electrode (105a) and a drain electrode (105b), which includes a first sub-layer (105-1), a second sub-layer (105-2), and a third sub-layer (105-3) sequentially disposed one over another. Both the third and the first sub-layers (105-3, 105-1) include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer (105-1) is greater than that in the third sub-layer (105-3).
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: July 28, 2020
    Assignees: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yi-Chun Kao, Hsin-Hua Lin, Po-Li Shih, Wei-Chih Chang, I-Min Lu, I-Wei Wu
  • Patent number: 10672880
    Abstract: A conductive layer for a thin film transistor (TFT) array panel includes a multi-layered portion defining a source electrode and a drain electrode of a TFT device, and includes a first sub-layer, a second sub-layer, a third sub-layer, and at least one additional sub-layer. The third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. An indium to zinc content ratio in the additional sub-layer is formulated between that in the first and the third sub-layers. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that in the first sub-layer.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: June 2, 2020
    Assignees: HONG FU JIN PRECISION INDUSTRY (SheZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Po-Li Shih, Yi-Chun Kao, Hsin-Hua Lin, Chih-Lung Lee, Wei-Chih Chang, I-Min Lu
  • Patent number: 10504927
    Abstract: A semiconductor device comprises a multi-layered structure disposed over a substrate (101) and defining a composite lateral etch profile. The multi-layered structure includes a lower sub-layer (105-1) disposed over the substrate (101) and comprising a metal oxide material that includes indium and zinc, the indium and zinc content in the lower sub-layer (105-1) substantially defining a first indium to zinc content ratio; a middle sub-layer (105-2) disposed over the lower sub-layer (105-1) and comprising a metal material; an upper sub-layer (105-3) disposed over the middle sub-layer (105-2) and comprising a metal oxide material that includes indium and zinc, the indium to zinc content in the upper sub-layer (105-3) substantially defining a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and a lateral byproduct layer formed over the lateral etched surface, comprising substantially an metal oxide of the metal material in the middle sub-layer (105-2).
    Type: Grant
    Filed: December 10, 2016
    Date of Patent: December 10, 2019
    Assignees: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yi-Chun Kao, Hsin-Hua Lin, Po-Li Shih, Wei-Chih Chang, I-Min Lu, I-Wei Wu
  • Publication number: 20190252418
    Abstract: An array substrate includes a substrate, a first insulator layer on the substrate, a second insulator layer on the first insulator layer, a third insulator layer on the second insulator layer, and a first TFT and a second TFT on the substrate. The second TFT includes a second gate electrode on the first insulator layer, a second channel layer on the second insulator layer, and a second source electrode and a second drain electrode on the third insulator layer. The third insulator layer covers the second channel layer and defines a second source hole and a second drain hole.
    Type: Application
    Filed: April 24, 2019
    Publication date: August 15, 2019
    Inventors: YI-CHUN KAO, HSIN-HUA LIN
  • Patent number: 10319752
    Abstract: An array substrate includes a substrate, a first insulator layer on the substrate, a second insulator layer on the first insulator layer, a third insulator layer on the second insulator layer, and a first TFT and a second TFT on the substrate. The second TFT includes a second gate electrode on the first insulator layer, a second channel layer on the second insulator layer, and a second source electrode and a second drain electrode on the third insulator layer. The third insulator layer covers the second channel layer and defines a second source hole and a second drain hole.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: June 11, 2019
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yi-Chun Kao, Hsin-Hua Lin
  • Patent number: 10276606
    Abstract: A method for making an array substrate includes the following steps: forming a poly-silicon semiconductor layer on a substrate; forming a buffer layer on the substrate; depositing a first metal layer, and patterning the first metal layer to form gate electrodes for a driving TFT, a switch TFT, and a poly-silicon TFT; forming a first gate insulator layer; forming a second gate insulator layer; defining through holes passing through the buffer layer, the first gate insulator layer, and the second gate insulator layer to expose the poly-silicon semiconductor layer; depositing a metal oxide layer to form a first metal oxide semiconductor layer; and depositing a second metal layer to form source electrodes and drain electrodes for the driving TFT, the switch TFT, and the poly-silicon TFT.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: April 30, 2019
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Hsin-Hua Lin, Yi-Chun Kao
  • Publication number: 20190109160
    Abstract: An array substrate includes a substrate, a first TFT, a second TFT, and a third TFT. The first TFT includes a first channel layer on the substrate, a first gate insulator layer, a first gate electrode, a first dielectric layer, and a second dielectric layer. The second TFT includes a first semiconductor layer on the substrate, a second gate insulator layer, a second gate electrode, a third dielectric layer, and a second channel layer. The first channel layer is made of a semiconducting material containing polycrystalline silicon. The second channel layer is made of a semiconducting material containing metal oxide. The first dielectric layer is made of silicon nitride; the second dielectric layer and the third dielectric layer are made of silicon oxide.
    Type: Application
    Filed: November 21, 2018
    Publication date: April 11, 2019
    Inventors: HSIN-HUA LIN, YI-CHUN KAO
  • Patent number: 10191338
    Abstract: An in-cell touch display apparatus which is proof against static electricity or the effects of its discharge includes a color filter structure, a thin film transistor (TFT) array structure with a touch electrode layer, and a ground portion. A liquid crystal layer is located between the color filter structure and the TFT array structure, a sealant is located between the color filter structure and the TFT array structure, and a protection layer is included. The protection layer directly contacts the sealant and the protection layer, the sealant, and the ground portion form a discharge path for discharging static electricity from the in-cell touch display apparatus.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: January 29, 2019
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chin-Yueh Liao, Yi-Chun Kao
  • Patent number: 10192897
    Abstract: An array substrate includes a substrate, a first TFT, a second TFT, and a third TFT. The first TFT includes a first channel layer on the substrate, a first gate insulator layer, a first gate electrode, a first dielectric layer, and a second dielectric layer. The second TFT includes a first semiconductor layer on the substrate, a second gate insulator layer, a second gate electrode, a third dielectric layer, and a second channel layer. The first channel layer is made of a semiconducting material containing polycrystalline silicon. The second channel layer is made of a semiconducting material containing metal oxide. The first dielectric layer is made of silicon nitride; the second dielectric layer and the third dielectric layer are made of silicon oxide.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: January 29, 2019
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Hsin-Hua Lin, Yi-Chun Kao
  • Publication number: 20190027571
    Abstract: A method of providing a conducting structure over a substrate, which comprises: disposing a lower sub-layer over a substrate, the lower sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and zinc content in the bottom sub-layer substantially defines a first indium to zinc content ratio; performing a first hydrogen treatment over an exposed surface of the lower sub-layer for introducing hydrogen content therein; disposing a middle sub-layer over the lower sub-layer, the middle sub-layer comprising a metal material; disposing an upper sub-layer over the middle sub-layer, the upper sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and the zinc content in the upper sub-layer substantially defines a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and patterning the multi-layered conductive structure to generate a composite lateral etch profile.
    Type: Application
    Filed: December 10, 2016
    Publication date: January 24, 2019
    Applicants: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: HSIN-HUA LIN, PO-LI SHIH, YI-CHUN KAO, CHANG-CHUN WAN, WEI-CHIH CHANG, I-WEI WU
  • Publication number: 20190027506
    Abstract: A conductive layer for a thin film transistor (TFT) array panel includes a multi-layered portion defining a source electrode and a drain electrode of a TFT device, and includes a first sub-layer, a second sub-layer, a third sub-layer, and at least one additional sub-layer. The third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. An indium to zinc content ratio in the additional sub-layer is formulated between that in the first and the third sub-layers. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that in the first sub-layer.
    Type: Application
    Filed: December 13, 2016
    Publication date: January 24, 2019
    Inventors: PO-LI SHIH, YI-CHUN KAO, HSIN-HUA LIN, CHIH-LUNG LEE, WEI-CHIH CHANG, I-MIN LU
  • Publication number: 20190027505
    Abstract: A semiconductor device comprises a multi-layered structure disposed over a substrate (101) and defining a composite lateral etch profile. The multi-layered structure includes a lower sub-layer (105-1) disposed over the substrate (101) and comprising a metal oxide material that includes indium and zinc, the indium and zinc content in the lower sub-layer (105-1) substantially defining a first indium to zinc content ratio; a middle sub-layer (105-2) disposed over the lower sub-layer (105-1) and comprising a metal material; an upper sub-layer (105-3) disposed over the middle sub-layer (105-2) and comprising a metal oxide material that includes indium and zinc, the indium to zinc content in the upper sub-layer (105-3) substantially defining a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and a lateral byproduct layer formed over the lateral etched surface, comprising substantially an metal oxide of the metal material in the middle sub-layer (105-2).
    Type: Application
    Filed: December 10, 2016
    Publication date: January 24, 2019
    Applicants: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Yi-Chun KAO, Hsin-Hua LIN, Po-Li SHIH, Wei-Chih CHANG, Imin LU, Iwei WU
  • Publication number: 20190019870
    Abstract: A thin film transistor array panel includes a first conductive layer (102) including a gate electrode; a channel layer (104) disposed over the gate; and a second conductive layer (105) disposed over the channel layer (104). The second conductive layer (105) includes a multi-layered portion defining a source electrode (105a) and a drain electrode (105b), which includes a first sub-layer (105-1), a second sub-layer (105-2), and a third sub-layer (105-3) sequentially disposed one over another. Both the third and the first sub-layers (105-3, 105-1) include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer (105-1) is greater than that in the third sub-layer (105-3).
    Type: Application
    Filed: December 7, 2016
    Publication date: January 17, 2019
    Applicants: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: YI-CHUN KAO, HSIN-HUA LIN, PO-LI SHIH, WEI-CHIH CHANG, I-MIN LU, I-WEI WU
  • Publication number: 20180374960
    Abstract: A high-performance TFT substrate (100) for a flat panel display includes a substrate (110), a first conductive layer (130) on the substrate (110), a semiconductor layer (103) positioned on the first conductive layer (130), and a second conductive layer (150) positioned on the semiconductor layer (103). The first conductive layer (130) defines a gate electrode (101). The second conductive layer (150) defines a source electrode (105) and a drain electrode (106) spaced apart from the source electrode (105). The second conductive layer (150) includes a first layer (151) on the semiconductor layer (103) and a second layer (152) positioned on the first layer (151). The first layer (151) can be made of metal oxide. The second layer (152) can be made of aluminum or aluminum alloy.
    Type: Application
    Filed: December 6, 2016
    Publication date: December 27, 2018
    Applicants: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: YI-CHUN KAO, PO-LI SHIH, WEI-CHIH CHANG, I-WEI WU
  • Patent number: 10079311
    Abstract: A TFT substrate includes a substrate and a plurality of TFTs on the substrate. Each TFT includes a channel layer, a source electrode and a drain electrode on opposite sides of the channel layer. An ohmic contact layer is applied between the channel layer and the source electrode, and between the channel layer and the drain electrode. Both the channel layer and the ohmic contact layer are made of a metal oxide containing zinc. The channel layer has a zinc atomic percentage of less than 35%, and the ohmic contact layer has a zinc atomic percentage of more than 65%.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: September 18, 2018
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Hsin-Hua Lin, Yi-Chun Kao
  • Patent number: 10062791
    Abstract: A thin film transistor comprises a substrate, a gate electrode formed on the substrate, an electrically insulating layer covering the gate electrode, a channel layer made of a semiconductor material and formed on the electrically insulating layer, a source electrode formed on a first lateral side of the electrically insulating layer, and a drain electrode formed on an opposite second lateral side of the electrically insulating layer. The source electrode has an inner end covering a first outer end of the channel layer and electrically connecting therewith. The drain electrode has an inner end covering an opposite second outer end of the channel layer and electrically connecting therewith. An area of the channel layer adjacent to and not covered by one of the source electrode and the drain electrode has an electrical conductivity lower than the electrical conductivity of other area of the channel layer.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: August 28, 2018
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Kuo-Lung Fang, Yi-Chun Kao, Po-Li Shih, Chih-Lung Lee, Hsin-Hua Lin
  • Publication number: 20180097116
    Abstract: A thin film transistor can include a substrate, a gate electrode on the substrate, a first electrode located on the substrate and surrounded by the gate electrode, a second electrode located on the first electrode and surrounded by the gate electrode, and a channel layer located between the first electrode and the second electrode. The gate electrode can include a first margin metal layer on the substrate and a second metal layer located on the first margin metal layer. A method for manufacturing the thin film transistor is also provided.
    Type: Application
    Filed: November 23, 2017
    Publication date: April 5, 2018
    Inventors: HSIN-HUA LIN, YI-CHUN KAO, CHIH-LUNG LEE, PO-LI SHIH, KUO-LUNG FANG
  • Patent number: 9905697
    Abstract: A high-performance TFT substrate for a flat panel display includes a substrate, a first conductive layer on the substrate, a semiconductor layer positioned on the first conductive layer, and a second conductive layer positioned on the semiconductor layer. The first conductive layer defines a gate electrode. The second conductive layer defines a source electrode and a drain electrode spaced apart from the source electrode. The second conductive layer includes a first layer on the semiconductor layer and a second layer positioned on the first layer. The first layer can be made of metal oxide. The second layer can be made of aluminum or aluminum alloy.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: February 27, 2018
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yi-Chun Kao, Po-Li Shih, Wei-Chih Chang, I-Wei Wu