Patents by Inventor YI-CHUN KAO

YI-CHUN KAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9905697
    Abstract: A high-performance TFT substrate for a flat panel display includes a substrate, a first conductive layer on the substrate, a semiconductor layer positioned on the first conductive layer, and a second conductive layer positioned on the semiconductor layer. The first conductive layer defines a gate electrode. The second conductive layer defines a source electrode and a drain electrode spaced apart from the source electrode. The second conductive layer includes a first layer on the semiconductor layer and a second layer positioned on the first layer. The first layer can be made of metal oxide. The second layer can be made of aluminum or aluminum alloy.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: February 27, 2018
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yi-Chun Kao, Po-Li Shih, Wei-Chih Chang, I-Wei Wu
  • Patent number: 9893197
    Abstract: A thin film transistor (TFT) includes a substrate, a TFT formed on the substrate, and a passivation layer formed on the TFT. The TFT includes a gate, a source, a drain, and a channel layer. The source and the drain are respectively located at opposite sides of the channel layer. The channel layer includes oxygen ions which are implanted into the channel layer by an oxygen implanting process performed in an environment having an air pressure greater than a standard atmospheric pressure.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: February 13, 2018
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yi-Chun Kao, Hsin-Hua Lin, Chih-Lung Lee, Kuo-Lung Fang, Po-Li Shih
  • Patent number: 9893198
    Abstract: A method for manufacturing a thin film transistor (TFT) which includes a gate, a gate insulation layer, a channel layer, an etching stopping layer, a source, and a drain. The gate is formed on a substrate. The gate insulation layer covers the gate and the substrate. The channel layer is formed on the gate insulation layer to correspond with the gate. The etching stopping layer is formed on a surface of the channel layer. The channel layer and the etching stopping layer are formed in a same photo etching process.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: February 13, 2018
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Kuo-Lung Fang, Yi-Chun Kao, Hsin-Hua Lin, Po-Li Shih, Chih-Lung Lee
  • Publication number: 20180040736
    Abstract: A TFT substrate includes a substrate and a plurality of TFTs on the substrate. Each TFT includes a channel layer, a source electrode and a drain electrode on opposite sides of the channel layer. An ohmic contact layer is applied between the channel layer and the source electrode, and between the channel layer and the drain electrode. Both the channel layer and the ohmic contact layer are made of a metal oxide containing zinc. The channel layer has a zinc atomic percentage of less than 35%, and the ohmic contact layer has a zinc atomic percentage of more than 65%.
    Type: Application
    Filed: August 2, 2017
    Publication date: February 8, 2018
    Inventors: HSIN-HUA LIN, YI-CHUN KAO
  • Publication number: 20180039145
    Abstract: An in-cell touch display apparatus which is proof against static electricity or the effects of its discharge includes a color filter structure, a thin film transistor (TFT) array structure with a touch electrode layer, and a ground portion. A liquid crystal layer is located between the color filter structure and the TFT array structure, a sealant is located between the color filter structure and the TFT array structure, and a protection layer is included. The protection layer directly contacts the sealant and the protection layer, the sealant, and the ground portion form a discharge path for discharging static electricity from the in-cell touch display apparatus.
    Type: Application
    Filed: August 4, 2017
    Publication date: February 8, 2018
    Inventors: CHIN-YUEH LIAO, YI-CHUN KAO
  • Publication number: 20180006065
    Abstract: A method for making an array substrate includes the following steps: forming a poly-silicon semiconductor layer on a substrate; forming a buffer layer on the substrate; depositing a first metal layer, and patterning the first metal layer to form gate electrodes for a driving TFT, a switch TFT, and a poly-silicon TFT; forming a first gate insulator layer; forming a second gate insulator layer; defining through holes passing through the buffer layer, the first gate insulator layer, and the second gate insulator layer to expose the poly-silicon semiconductor layer; depositing a metal oxide layer to form a first metal oxide semiconductor layer; and depositing a second metal layer to form source electrodes and drain electrodes for the driving TFT, the switch TFT, and the poly-silicon TFT.
    Type: Application
    Filed: August 18, 2017
    Publication date: January 4, 2018
    Inventors: HSIN-HUA LIN, YI-CHUN KAO
  • Patent number: 9859440
    Abstract: A thin film transistor can include a substrate, a gate electrode on the substrate, a first electrode located on the substrate and surrounded by the gate electrode, a second electrode located on the first electrode and surrounded by the gate electrode, and a channel layer located between the first electrode and the second electrode. The gate electrode can include a first margin metal layer on the substrate and a second metal layer located on the first margin metal layer. A method for manufacturing the thin film transistor is also provided.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: January 2, 2018
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Hsin-Hua Lin, Yi-Chun Kao, Chih-Lung Lee, Po-Li Shih, Kuo-Lung Fang
  • Patent number: 9853057
    Abstract: A display array substrate includes a substrate, a plurality of gate lines and a plurality of data lines disposed on the substrate, and a plurality of gate connecting pads. Each gate connecting pad is disposed at an end of one of the gate lines. The end of each gate line is partly covered by a first insulation layer. The first insulation layer is an anodic oxide layer.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: December 26, 2017
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Po-Li Shih, Yi-Chun Kao
  • Patent number: 9823528
    Abstract: An array substrate for a liquid crystal display device includes a first storage capacitor and a second storage capacitor for increased capacitance. The first storage capacitor is formed by a first common electrode and a pixel electrode. The second storage capacitor is formed by a second common electrode and the pixel electrode.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: November 21, 2017
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Wu-Liu Tsai, Yi-Chun Kao, Hsin-Hua Lin, Po-Li Shih, Chih-Lung Lee
  • Patent number: 9806179
    Abstract: A method of providing a conducting structure over a substrate, which comprises: disposing a lower sub-layer over a substrate, the lower sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and zinc content in the bottom sub-layer substantially defines a first indium to zinc content ratio; performing a first hydrogen treatment over an exposed surface of the lower sub-layer for introducing hydrogen content therein; disposing a middle sub-layer over the lower sub-layer, the middle sub-layer comprising a metal material; disposing an upper sub-layer over the middle sub-layer, the upper sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and the zinc content in the upper sub-layer substantially defines a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and patterning the multi-layered conductive structure to generate a composite lateral etch profile.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: October 31, 2017
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Hsin-Hua Lin, Po-Li Shih, Yi-Chun Kao, Chang-Chun Wan, Wei-Chih Chang, I-Wei Wu
  • Patent number: 9799680
    Abstract: A TFT array substrate includes a plurality of scan lines, a plurality of date lines, a plurality of pixels, a first TFT, and a second TFT. The number of scan lines includes a first scan line. The date lines are insulated with the scan lines include a first date line and a second date line. The first date line is insulated and at least partly covering the second date line. The pixels are defined by two adjacent scan lines and two adjacent date lines. The first TFT is configured to drive a first pixel at the first side of the first scan line and being coupled with the first scan line and the first date line. The second TFT is configured to drive a second pixel at the second side of the first scan line and being coupled with the first scan line and the second date line.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: October 24, 2017
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yi-Chun Kao, Hsin-Hua Lin, Po-Li Shih, Chih-Lung Lee
  • Patent number: 9793409
    Abstract: A semiconductor device comprises a multi-layered structure disposed over a substrate and defining a composite lateral etch profile. The multi-layered structure includes a lower sub-layer disposed over the substrate and comprising a metal oxide material that includes indium and zinc, the indium and zinc content in the bottom sub-layer substantially defining a first indium to zinc content ratio; a middle sub-layer disposed over the bottom sub-layer and comprising a metal material; an upper sub-layer disposed over the middle sub-layer and comprising a metal oxide material that includes indium and zinc, the indium to zinc content in the upper sub-layer substantially defining a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and a lateral byproduct layer formed over the lateral etched surface, comprising substantially an metal oxide of the metal material in the middle sub-layer.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: October 17, 2017
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yi-Chun Kao, Hsin-Hua Lin, Po-Li Shih, Wei-Chih Chang, I-Min Lu, I-Wei Wu
  • Patent number: 9768204
    Abstract: An array substrate includes a substrate, driving TFTs, and switch TFTs directly on the substrate. The driving TFT includes a buffer layer, a gate, a first gate insulator layer, a second gate insulator layer, and a metal oxide semiconductor layer stacked in that order on the substrate, and a source electrode and a drain electrode coupled to the metal oxide semiconductor layer. The switch TFT includes a buffer layer, a gate, a second gate insulator layer, and a metal oxide semiconductor layer stacked in that order on the substrate, and a source electrode and a drain electrode coupled to the metal oxide semiconductor layer.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: September 19, 2017
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Hsin-Hua Lin, Yi-Chun Kao
  • Patent number: 9741862
    Abstract: A thin film transistor (TFT) includes a gate, a gate insulation layer, a channel, a source, and a drain. The gate is formed on a substrate. The gate insulation layer covers the gate and the substrate. The channel layer is formed on the gate insulation layer to correspond with the gate. The source and a drain are respectively coupled at opposite sides of the channel layer. The channel layer includes a conductor layer and a semiconductor layer. The semiconductor layer includes a first portion and a second portion respectively coupled at opposite sides of the conductor layer.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: August 22, 2017
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Po-Li Shih, Yi-Chun Kao, Chih-Lung Lee, Hsin-Hua Lin, Kuo-Lung Fang
  • Patent number: 9728650
    Abstract: A thin film transistor array panel includes a first conductive layer including a gate electrode; a channel layer disposed over the gate; and a second conductive layer disposed over the channel layer. The second conductive layer includes a multi-layered portion defining a source electrode and a drain electrode, which includes a first sub-layer, a second sub-layer, and a third sub-layer sequentially disposed one over another. Both the third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that that in the first sub-layer.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: August 8, 2017
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yi-Chun Kao, Hsin-Hua Lin, Po-Li Shih, Wei-Chih Chang, I-Min Lu, I-Wei Wu
  • Publication number: 20170207325
    Abstract: A method of providing a conducting structure over a substrate, which comprises: disposing a lower sub-layer over a substrate, the lower sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and zinc content in the bottom sub-layer substantially defines a first indium to zinc content ratio; performing a first hydrogen treatment over an exposed surface of the lower sub-layer for introducing hydrogen content therein; disposing a middle sub-layer over the lower sub-layer, the middle sub-layer comprising a metal material; disposing an upper sub-layer over the middle sub-layer, the upper sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and the zinc content in the upper sub-layer substantially defines a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and patterning the multi-layered conductive structure to generate a composite lateral etch profile.
    Type: Application
    Filed: March 15, 2016
    Publication date: July 20, 2017
    Inventors: HSIN-HUA LIN, PO-LI SHIH, YI-CHUN KAO, CHANG-CHUN WAN, WEI-CHIH CHANG, I-WEI WU
  • Publication number: 20170207243
    Abstract: A semiconductor device comprises a multi-layered structure disposed over a substrate and defining a composite lateral etch profile. The multi-layered structure includes a lower sub-layer disposed over the substrate and comprising a metal oxide material that includes indium and zinc, the indium and zinc content in the bottom sub-layer substantially defining a first indium to zinc content ratio; a middle sub-layer disposed over the bottom sub-layer and comprising a metal material; an upper sub-layer disposed over the middle sub-layer and comprising a metal oxide material that includes indium and zinc, the indium to zinc content in the upper sub-layer substantially defining a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and a lateral byproduct layer formed over the lateral etched surface, comprising substantially an metal oxide of the metal material in the middle sub-layer.
    Type: Application
    Filed: March 31, 2016
    Publication date: July 20, 2017
    Inventors: YI-CHUN KAO, HSIN-HUA LIN, PO-LI SHIH, WEI-CHIH CHANG, I-MIN LU, I-WEI WU
  • Publication number: 20170207342
    Abstract: A thin film transistor array panel includes a first conductive layer including a gate electrode; a channel layer disposed over the gate; and a second conductive layer disposed over the channel layer. The second conductive layer includes a multi-layered portion defining a source electrode and a drain electrode, which includes a first sub-layer, a second sub-layer, and a third sub-layer sequentially disposed one over another. Both the third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that that in the first sub-layer.
    Type: Application
    Filed: March 15, 2016
    Publication date: July 20, 2017
    Inventors: YI-CHUN KAO, HSIN-HUA LIN, PO-LI SHIH, WEI-CHIH CHANG, I-MIN LU, I-WEI WU
  • Publication number: 20170179300
    Abstract: A high-performance TFT substrate for a flat panel display includes a substrate, a first conductive layer on the substrate, a semiconductor layer positioned on the first conductive layer, and a second conductive layer positioned on the semiconductor layer. The first conductive layer defines a gate electrode. The second conductive layer defines a source electrode and a drain electrode spaced apart from the source electrode. The second conductive layer includes a first layer on the semiconductor layer and a second layer positioned on the first layer. The first layer can be made of metal oxide. The second layer can be made of aluminum or aluminum alloy.
    Type: Application
    Filed: October 19, 2016
    Publication date: June 22, 2017
    Inventors: YI-CHUN KAO, PO-LI SHIH, WEI-CHIH CHANG, I-WEI WU
  • Patent number: 9634147
    Abstract: A thin film transistor (TFT) array substrate of a liquid crystal display (LCD) panel includes a first substrate, a gate located on the first substrate, a gate insulation layer located on the first substrate and covers the gate and the first substrate, a source layer located on the gate insulation layer to correspond to the gate, an etching stopping layer located on the source layer, and a source and a drain located on the etching stopping layer. The etching stopping layer is made of color photoresist.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: April 25, 2017
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Hsin-Hua Lin, Yi-Chun Kao