Patents by Inventor YI-CHUN KAO

YI-CHUN KAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170084641
    Abstract: An array substrate includes a substrate, and a first TFT and a second TFT on the substrate. The second TFT is a low-temperature poly silicon TFT. The first TFT includes a buffer layer, a gate, a gate insulator layer, and a metal oxide semiconductor layer stacked on the substrate in that order. A source electrode and a drain electrode are separately positioned on the gate insulator layer and coupled to the metal oxide semiconductor layer of the first TFT. The metal oxide semiconductor layer partially covers the source electrode and the drain electrode.
    Type: Application
    Filed: June 30, 2016
    Publication date: March 23, 2017
    Inventors: HSIN-HUA LIN, YI-CHUN KAO
  • Publication number: 20170084636
    Abstract: An array substrate includes a substrate, driving TFTs, and switch TFTs directly on the substrate. The driving TFT includes a buffer layer, a gate, a first gate insulator layer, a second gate insulator layer, and a metal oxide semiconductor layer stacked in that order on the substrate, and a source electrode and a drain electrode coupled to the metal oxide semiconductor layer. The switch TFT includes a buffer layer, a gate, a second gate insulator layer, and a metal oxide semiconductor layer stacked in that order on the substrate, and a source electrode and a drain electrode coupled to the metal oxide semiconductor layer.
    Type: Application
    Filed: June 28, 2016
    Publication date: March 23, 2017
    Inventors: HSIN-HUA LIN, YI-CHUN KAO
  • Publication number: 20170084639
    Abstract: An array substrate includes a substrate, a first insulator layer on the substrate, a second insulator layer on the first insulator layer, a third insulator layer on the second insulator layer, and a first TFT and a second TFT on the substrate. The second TFT includes a second gate electrode on the first insulator layer, a second channel layer on the second insulator layer, and a second source electrode and a second drain electrode on the third insulator layer. The third insulator layer covers the second channel layer and defines a second source hole and a second drain hole.
    Type: Application
    Filed: August 31, 2016
    Publication date: March 23, 2017
    Inventors: YI-CHUN KAO, HSIN-HUA LIN
  • Publication number: 20170084642
    Abstract: An array substrate includes a substrate, a first TFT, a second TFT, and a third TFT. The first TFT includes a first channel layer on the substrate, a first gate insulator layer, a first gate electrode, a first dielectric layer, and a second dielectric layer. The second TFT includes a first semiconductor layer on the substrate, a second gate insulator layer, a second gate electrode, a third dielectric layer, and a second channel layer. The first channel layer is made of a semiconducting material containing polycrystalline silicon. The second channel layer is made of a semiconducting material containing metal oxide. The first dielectric layer is made of silicon nitride; the second dielectric layer and the third dielectric layer are made of silicon oxide.
    Type: Application
    Filed: August 31, 2016
    Publication date: March 23, 2017
    Inventors: HSIN-HUA LIN, YI-CHUN KAO
  • Patent number: 9576984
    Abstract: A conductive layer for a thin film transistor (TFT) array panel includes a multi-layered portion defining a source electrode and a drain electrode of a TFT device, and includes a first sub-layer, a second sub-layer, a third sub-layer, and at least one additional sub-layer. The third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. An indium to zinc content ratio in the additional sub-layer is formulated between that in the first and the third sub-layers. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that that in the first sub-layer.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: February 21, 2017
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Po-Li Shih, Yi-Chun Kao, Hsin-Hua Lin, Chih-Lung Lee, Wei-Chih Chang, I-Min Lu
  • Patent number: 9576990
    Abstract: A thin film transistor includes a substrate, a gate electrode formed on the substrate, an electrically insulating layer formed on the substrate and covering the gate electrode, a channel layer made of semiconductor material and formed on the electrically insulating layer, an etch stop pattern formed on the channel layer and defining a first through hole and a second through hole; and a source electrode and a drain electrode formed on the etch stop pattern. The source electrode extends into the first through hole to electrically couple to the channel layer. The drain electrode extends into the second through hole to electrically couple to the channel layer. Both the channel layer and the etch stop pattern are formed by using a single mask and a single photoresist layer.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: February 21, 2017
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Kuo-Lung Fang, Yi-Chun Kao, Hsin-Hua Lin, Chih-Lung Lee, Po-Li Shih
  • Patent number: 9548392
    Abstract: A method for manufacturing a thin film transistor include following steps. A substrate is provided. A gate electrode and an electrically insulating layer are formed on the substrate. An electric conducting layer is formed on the electrically insulating layer. A first photoresist pattern layer is formed on the electric conducting layer. A portion of the electric conducting layer which is not covered by the first photoresist pattern layer is etched to form an electric conduction layer. A semiconductor layer is formed on the electric conduction layer. A second photoresist pattern layer is formed. A portion of the semiconductor layer which is not covered by the second photoresist pattern layer is etched to form the channel layer covering the electric conduction layer. A source electrode and a drain electrode are formed at the two lateral portions of the channel layer respectively. The thin film transistor is also provided.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: January 17, 2017
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Po-Li Shih, Yi-Chun Kao, Chih-Lung Lee, Kuo-Lung Fang, Hsin-Hua Lin
  • Publication number: 20160351719
    Abstract: A method for manufacturing a thin film transistor include following steps. A substrate is provided. A gate electrode and an electrically insulating layer are formed on the substrate. An electric conducting layer is formed on the electrically insulating layer. A first photoresist pattern layer is formed on the electric conducting layer. A portion of the electric conducting layer which is not covered by the first photoresist pattern layer is etched to form an electric conduction layer. A semiconductor layer is formed on the electric conduction layer. A second photoresist pattern layer is formed. A portion of the semiconductor layer which is not covered by the second photoresist pattern layer is etched to form the channel layer covering the electric conduction layer. A source electrode and a drain electrode are formed at the two lateral portions of the channel layer respectively. The thin film transistor is also provided.
    Type: Application
    Filed: August 25, 2015
    Publication date: December 1, 2016
    Inventors: PO-LI SHIH, YI-CHUN KAO, CHIH-LUNG LEE, KUO-LUNG FANG, HSIN-HUA LIN
  • Publication number: 20160351717
    Abstract: A thin film transistor (TFT) includes a gate, a gate insulation layer, a channel, a source, and a drain. The gate is formed on a substrate. The gate insulation layer covers the gate and the substrate. The channel layer is formed on the gate insulation layer to correspond with the gate. The source and a drain are respectively coupled at opposite sides of the channel layer. The channel layer includes a conductor layer and a semiconductor layer. The semiconductor layer includes a first portion and a second portion respectively coupled at opposite sides of the conductor layer.
    Type: Application
    Filed: July 7, 2015
    Publication date: December 1, 2016
    Inventors: PO-LI SHIH, YI-CHUN KAO, CHIH-LUNG LEE, HSIN-HUA LIN, KUO-LUNG FANG
  • Publication number: 20160343865
    Abstract: A method for manufacturing a thin film transistor (TFT) which includes a gate, a gate insulation layer, a channel layer, an etching stopping layer, a source, and a drain. The gate is formed on a substrate. The gate insulation layer covers the gate and the substrate. The channel layer is formed on the gate insulation layer to correspond with the gate. The etching stopping layer is formed on a surface of the channel layer. The channel layer and the etching stopping layer are formed in a same photo etching process.
    Type: Application
    Filed: June 30, 2015
    Publication date: November 24, 2016
    Inventors: KUO-LUNG FANG, YI-CHUN KAO, HSIN-HUA LIN, PO-LI SHIH, CHIH-LUNG LEE
  • Publication number: 20160343738
    Abstract: A method for manufacturing a thin film transistor (TFT), the TFT includes a gate, a first insulation layer, a channel layer, a source, a drain, a second insulation, and a flat layer. The gate is formed on a base. The first insulation layer is formed on the base to cover the gate and the base. The channel layer is formed on the first insulation layer corresponding to the gate. The second insulation layer is formed on the base to cover the first insulation layer, the channel layer, the source, and the drain. The flat layer includes a first region and a second region and is formed on the second insulation layer. The first region and the second region respectively have different light transmittance.
    Type: Application
    Filed: August 24, 2015
    Publication date: November 24, 2016
    Inventors: YI-CHUN KAO, HSIN-HUA LIN, CHIH-LUNG LEE, KUO-LUNG FANG, PO-LI SHIH
  • Publication number: 20160329362
    Abstract: A thin film transistor includes a substrate, a gate electrode formed on the substrate, an electrically insulating layer formed on the substrate and covering the gate electrode, a channel layer made of semiconductor material and formed on the electrically insulating layer, an etch stop pattern formed on the channel layer and defining a first through hole and a second through hole; and a source electrode and a drain electrode formed on the etch stop pattern. The source electrode extends into the first through hole to electrically couple to the channel layer. The drain electrode extends into the second through hole to electrically couple to the channel layer. Both the channel layer and the etch stop pattern are formed by using a single mask and a single photoresist layer.
    Type: Application
    Filed: July 21, 2016
    Publication date: November 10, 2016
    Inventors: KUO-LUNG FANG, YI-CHUN KAO, HSIN-HUA LIN, CHIH-LUNG LEE, PO-LI SHIH
  • Publication number: 20160329351
    Abstract: A display array substrate includes a substrate, a plurality of gate lines and a plurality of data lines disposed on the substrate, and a plurality of gate connecting pads. Each gate connecting pad is disposed at an end of one of the gate lines. The end of each gate line is partly covered by a first insulation layer. The first insulation layer is an anodic oxide layer.
    Type: Application
    Filed: July 19, 2016
    Publication date: November 10, 2016
    Inventors: PO-LI SHIH, YI-CHUN KAO
  • Patent number: 9478669
    Abstract: A thin film transistor includes a gate electrode, a gate insulating layer, a channel layer, an etching stop layer, two contact holes, a source, and a drain. The gate insulating layer covers the gate electrode. The channel layer is arranged on the gate insulating layer corresponding to the gate electrode. The etching stop layer covers the channel layer and includes an organic stop layer and a hard mask layer, the hard mask layer is located on a surface of the organic stop layer opposite to the channel layer to enhance a hardness of the organic stop layer. The two contact holes pass through the etching stop layer. The source connects to the channel via one contact hole, and the drain connects to the channel via the other contact hole.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: October 25, 2016
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: I-Wei Wu, I-Min Lu, Wei-Chih Chang, Hui-Chu Lin, Yi-Chun Kao, Kuo-Lung Fang
  • Patent number: 9472674
    Abstract: A thin film transistor includes a first gate electrode located on a base, a second gate electrode located on the base, an insulating layer, a source electrode, a drain electrode, and a channel layer. The insulating layer covers the base, the first gate electrode, and the second gate electrode. The second gate electrode is insulated from the first gate electrode. The channel layer includes a first portion and a second portion sandwiched between the first portion and the insulating layer. A conductivity of the second portion is larger than a conductivity of the first portion. The first portion includes a first region facing the first gate electrode and a second region facing the second gate electrode. The source electrode is electrically connected to the first region, and the drain electrode is electrically connected to the second region.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: October 18, 2016
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Kuo-Lung Fang, Po-Li Shih, Yi-Chun Kao, Hsin-Hua Lin, Chih-Lung Lee
  • Patent number: 9450077
    Abstract: A method of manufacturing a thin film transistor substrate is provided, including a first photoresist pattern covers a channel during a process of etching a second photoresist pattern and protects the channel. Thus, an etching stop layer is not required.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: September 20, 2016
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Kuo-Lung Fang, Yi-Chun Kao, Po-Li Shih, Chih-Lung Lee, Hsin-Hua Lin
  • Publication number: 20160268444
    Abstract: A thin film transistor comprises a substrate, a gate electrode formed on the substrate, an electrically insulating layer covering the gate electrode, a channel layer made of a semiconductor material and formed on the electrically insulating layer, a source electrode formed on a first lateral side of the electrically insulating layer, and a drain electrode formed on an opposite second lateral side of the electrically insulating layer. The source electrode has an inner end covering a first outer end of the channel layer and electrically connecting therewith. The drain electrode has an inner end covering an opposite second outer end of the channel layer and electrically connecting therewith. An area of the channel layer adjacent to and not covered by one of the source electrode and the drain electrode has an electrical conductivity lower than the electrical conductivity of other area of the channel layer.
    Type: Application
    Filed: May 23, 2016
    Publication date: September 15, 2016
    Inventors: KUO-LUNG FANG, YI-CHUN KAO, PO-LI SHIH, CHIH-LUNG LEE, HSIN-HUA LIN
  • Patent number: 9437750
    Abstract: A method for forming a TFT includes providing a substrate, and forming a gate electrode, an electrically insulating layer, a semiconductor layer, an etch stop layer and a photoresist layer successively on the substrate. A photolithographic process is performed to the photoresist layer by using a half-tone mask to thereby configure the photoresist layer to have two recesses in a top thereof. Two lateral ends of the etch stop layer are etched away to form an etch stop pattern. The photoresist layer is heated to flow downwardly. Two lateral ends of the semiconductor channel are etched away to become a channel layer. An ashing is performed to the photoresist layer to have the recesses thereof communicate atmosphere with the etch stop pattern. The etch stop pattern is etched to define first and second through holes. Source and drain electrodes are formed to electrically connect with the channel layer.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: September 6, 2016
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Kuo-Lung Fang, Yi-Chun Kao, Hsin-Hua Lin, Chih-Lung Lee, Po-Li Shih
  • Patent number: 9425294
    Abstract: A manufacturing method of display array substrate is provided. The method includes depositing a first metal layer on a substrate and defining a peripheral area and a display area, coating a photo-resist layer on the first metal layer located in the peripheral area, anodizing the first metal layer to a first metal oxide layer with the photo-resist layer as a mask, patterning the first metal oxide layer located in the display area to a gate insulator, removing the photo-resist layer to expose the first metal layer in the peripheral area, forming a channel layer on the gate insulator, and depositing a second metal layer and patterning the second metal layer located in the display area to form a source electrode and a drain electrode.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: August 23, 2016
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Po-Li Shih, Yi-Chun Kao
  • Publication number: 20160190327
    Abstract: A thin film transistor (TFT) includes a substrate, a TFT formed on the substrate, and a passivation layer formed on the TFT. The TFT includes a gate, a source, a drain, and a channel layer. The source and the drain are respectively located at opposite sides of the channel layer. The channel layer includes oxygen ions which are implanted into the channel layer by an oxygen implanting process performed in an environment having an air pressure greater than a standard atmospheric pressure.
    Type: Application
    Filed: June 26, 2015
    Publication date: June 30, 2016
    Inventors: YI-CHUN KAO, HSIN-HUA LIN, CHIH-LUNG LEE, KUO-LUNG FANG, PO-LI SHIH