Patents by Inventor Yi-Chun Lo
Yi-Chun Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11956541Abstract: A control method of a driving mechanism is provided, including: the driving mechanism provides a first electrical signal from a control assembly to the driving mechanism to move the movable portion into an initial position relative to the fixed portion, wherein the control assembly includes a control unit and a position sensing unit; the status signal of an inertia sensing unit is read; the control unit sends the status signal to the control unit to calculate a target position; the control unit provides a second electrical signal to the driving assembly according to the target position for driving the driving assembly; a position signal is sent from the position sensing unit to the control unit; the control unit provides a third electric signal to the driving assembly to drive the driving assembly according the position signal.Type: GrantFiled: January 26, 2023Date of Patent: April 9, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chen-Hsien Fan, Sung-Mao Tsai, Yueh-Lin Lee, Yu-Chiao Lo, Mao-Kuo Hsu, Ching-Chieh Huan, Yi-Chun Cheng
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Publication number: 20240077479Abstract: A detection system and method for the migrating cell is provided. The system is configured to detect a migrating cell combined with an immunomagnetic bead. The system includes a platform, a microchannel, a magnetic field source, a coherent light source and an optical sensing module. The microchannel is configured to allow the migrating cell to flow in it along a flow direction. The magnetic field source is configured to provide magnetic force to the migrating cell combined with the immunomagnetic bead. The magnetic force includes at least one magnetic force component and the magnetic force component is opposite to the flow direction of the microchannel. The coherent light source is configured to provide the microchannel with the coherent light. The optical sensing module is configured to receive the interference light caused by the coherent light being reflected by the sample inside the microchannel.Type: ApplicationFiled: August 10, 2023Publication date: March 7, 2024Applicant: DeepBrain Tech. IncInventors: Han-Lin Wang, Chia-Wei Chen, Yao-Wen Liang, Ting-Chun Lin, Yun-Ting Kuo, You-Yin Chen, Yu-Chun Lo, Ssu-Ju Li, Ching-Wen Chang, Yi-Chen Lin
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Publication number: 20220231143Abstract: A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion.Type: ApplicationFiled: April 4, 2022Publication date: July 21, 2022Inventors: Bo-Wen HSIEH, Yi-Chun LO, Wen-Jia HSIEH
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Patent number: 11296201Abstract: A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion.Type: GrantFiled: June 15, 2020Date of Patent: April 5, 2022Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Bo-Wen Hsieh, Yi-Chun Lo, Wen-Jia Hsieh
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Publication number: 20210305387Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate stack structure formed over a substrate. The gate stack structure includes a gate electrode structure having a first portion and a second portion and a first conductive layer below the gate electrode structure. In addition, the first portion of the gate electrode structure is located over the second portion of the gate electrode structure, and a width of a top surface of the first portion of the gate electrode structure is greater than a width of a bottom surface of the second portion of the gate electrode structure.Type: ApplicationFiled: June 14, 2021Publication date: September 30, 2021Inventors: Bo-Wen HSIEH, Wen-Jia HSIEH, Yi-Chun LO, Mi-Hua LIN
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Patent number: 11038035Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate stack structure formed over a substrate. The gate stack structure includes a gate electrode structure having a first portion and a second portion and a first conductive layer below the gate electrode structure. In addition, the first portion of the gate electrode structure is located over the second portion of the gate electrode structure, and a width of a top surface of the first portion of the gate electrode structure is greater than a width of a bottom surface of the second portion of the gate electrode structure.Type: GrantFiled: November 20, 2018Date of Patent: June 15, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Bo-Wen Hsieh, Wen-Jia Hsieh, Yi-Chun Lo, Mi-Hua Lin
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Publication number: 20200312972Abstract: A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion.Type: ApplicationFiled: June 15, 2020Publication date: October 1, 2020Inventors: Bo-Wen HSIEH, Yi-Chun LO, Wen-Jia HSIEH
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Patent number: 10686049Abstract: A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion.Type: GrantFiled: June 3, 2019Date of Patent: June 16, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Bo-Wen Hsieh, Yi-Chun Lo, Wen-Jia Hsieh
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Publication number: 20190288085Abstract: A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion.Type: ApplicationFiled: June 3, 2019Publication date: September 19, 2019Inventors: Bo-Wen HSIEH, Yi-Chun LO, Wen-Jia HSIEH
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Patent number: 10312338Abstract: A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion.Type: GrantFiled: June 22, 2018Date of Patent: June 4, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Bo-Wen Hsieh, Yi-Chun Lo, Wen-Jia Hsieh
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Patent number: 10262894Abstract: Provided is a FinFET device including a substrate having at least one fin of the FinFET device, a gate stack, a spacer, a strained layer, a composite etching stop layer, a dielectric layer and a connector. The gate stack is across the at least one fin of the FinFET device. The spacer is on a sidewall of the gate stack. The strained layer is in the substrate aside the gate stack. The composite etching stop layer is on the spacer and on the strained layer. Besides, the composite etching stop layer is thicker on the spacer but thinner on the strained layer. The dielectric layer is on the composite etching stop layer. The connector is over and electrically connected to the strained layer. A first upper portion of a first sidewall of the connector is in contact with the composite etching stop layer, and a second upper portion of a second sidewall of the connector is separate from the composite etching stop layer by the dielectric layer therebetween.Type: GrantFiled: February 5, 2018Date of Patent: April 16, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Jia Hsieh, Yi-Chun Lo
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Publication number: 20190109198Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate stack structure formed over a substrate. The gate stack structure includes a gate electrode structure having a first portion and a second portion and a first conductive layer below the gate electrode structure. In addition, the first portion of the gate electrode structure is located over the second portion of the gate electrode structure, and a width of a top surface of the first portion of the gate electrode structure is greater than a width of a bottom surface of the second portion of the gate electrode structure.Type: ApplicationFiled: November 20, 2018Publication date: April 11, 2019Inventors: Bo-Wen HSIEH, Wen-Jia HSIEH, Yi-Chun LO, Mi-Hua LIN
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Patent number: 10170554Abstract: A semiconductor device includes: a gate structure on a substrate; a raised source/drain region adjacent to the gate structure; a channel region under the gate structure; and a protection layer between the substrate and the raised source/drain region. The protection layer is interposed between the substrate and the raised source/drain region. An atom stacking arrangement of the protection layer is different from the substrate and the raised source/drain region.Type: GrantFiled: December 26, 2014Date of Patent: January 1, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wen-Jia Hsieh, Hsin-Hung Chen, Yi-Chun Lo, Jung-You Chen
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Patent number: 10141416Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate stack structure formed over a substrate. The gate stack structure includes a gate electrode structure having a first portion and a second portion and a first conductive layer below the gate electrode structure. In addition, the first portion of the gate electrode structure is located over the second portion of the gate electrode structure, and a width of a top surface of the first portion of the gate electrode structure is greater than a width of a bottom surface of the second portion of the gate electrode structure.Type: GrantFiled: August 25, 2017Date of Patent: November 27, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Bo-Wen Hsieh, Wen-Jia Hsieh, Yi-Chun Lo, Mi-Hua Lin
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Patent number: 10124301Abstract: The filtration material includes a supporting layer, a first selective layer disposed on the supporting layer, and a second selective layer disposed on the first selective layer. The first selective layer includes a polyimide and an ionic polymer intertwined with the polyimide. In particular, the polyimide includes at least one repeat unit having a structure represented by Formula (I) wherein A1 is A2 is R1 and R2 are independently —H, —CF3, —OH, —Br, —Cl, —F, C1-6 alkyl group, or C1-6 alkoxy group; and X and Y are independently single bond, —O—, —CH2—, —C(CH3)2—, or —NH—.Type: GrantFiled: July 18, 2016Date of Patent: November 13, 2018Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Rui-Xuan Dong, Shu-Hui Cheng, Jen-You Chu, Yin-Ju Yang, Yi-Chun Lo
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Publication number: 20180323270Abstract: A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion.Type: ApplicationFiled: June 22, 2018Publication date: November 8, 2018Inventors: Bo-Wen HSIEH, Yi-Chun LO, Wen-Jia HSEIH
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Patent number: 10008574Abstract: A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion.Type: GrantFiled: October 13, 2016Date of Patent: June 26, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Bo-Wen Hsieh, Wen-Jia Hsieh, Yi-Chun Lo
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Publication number: 20180158729Abstract: Provided is a FinFET device including a substrate having at least one fin of the FinFET device, a gate stack, a spacer, a strained layer, a composite etching stop layer, a dielectric layer and a connector. The gate stack is across the at least one fin of the FinFET device. The spacer is on a sidewall of the gate stack. The strained layer is in the substrate aside the gate stack. The composite etching stop layer is on the spacer and on the strained layer. Besides, the composite etching stop layer is thicker on the spacer but thinner on the strained layer. The dielectric layer is on the composite etching stop layer. The connector is over and electrically connected to the strained layer. A first upper portion of a first sidewall of the connector is in contact with the composite etching stop layer, and a second upper portion of a second sidewall of the connector is separate from the composite etching stop layer by the dielectric layer therebetween.Type: ApplicationFiled: February 5, 2018Publication date: June 7, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Jia Hsieh, Yi-Chun Lo
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Patent number: 9887130Abstract: Provided is a FinFET device including a substrate having at least one fin, a gate stack, a spacer, a strained layer and a composite etching stop layer. The gate stack is across the at least one fin. The spacer is on a sidewall of the gate stack. The strained layer is in the substrate aside the gate stack. The composite etching stop layer is on the spacer and on the strained layer. Besides, the composite etching stop layer is thicker on the spacer but thinner on the strained layer.Type: GrantFiled: January 29, 2016Date of Patent: February 6, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Jia Hsieh, Yi-Chun Lo
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Patent number: 9853832Abstract: The present disclosure provides a wireless Ethernet network controlling method, for connecting a mobile device to an Ethernet through a wireless dock, comprising: connecting an Ethernet PHY of a wireless dock to an Ethernet; wirelessly linking a first wireless NIC of the wireless dock to a second wireless NIC of a mobile device; a control server unit of the wireless dock receiving an operation status setting signal through the first wireless NIC generated by a virtual Ethernet NIC, and the control server unit transmitting the operation status setting signal to the Ethernet PHY for setting-up the operation status of the Ethernet PHY; and a VLAN unit processing the data packets transmitted between the Ethernet PHY and the first wireless NIC. Accordingly, the user of the mobile device can experience the complete functions of the Ethernet device.Type: GrantFiled: March 17, 2015Date of Patent: December 26, 2017Assignee: UNIVERSAL SCIENTIFIC INDUSTRIAL (SHANGHAI) CO., LTD.Inventors: Chih-Chun Chen, Yi-Chun Lo