Patents by Inventor Yi-Chung Liang

Yi-Chung Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230029739
    Abstract: A semiconductor device includes a pair of fin structures on a semiconductor substrate, each including a vertically stacked plurality of channel layers, a dielectric fin extending in parallel to and between the fin structures, and a gate structure on and extending perpendicularly to the fin structures, the gate structure engaging with the plurality of channel layers. The dielectric fin includes a fin bottom and a fin top over the fin bottom. The fin bottom has a top surface extending above a bottom surface of a topmost channel layer. The fin top includes a core and a shell, the core having a first dielectric material, the shell surrounding the core and having a second dielectric material different from the first dielectric material.
    Type: Application
    Filed: July 29, 2021
    Publication date: February 2, 2023
    Inventors: Chih-Chung Chang, Sung-En Lin, Chung-Ting Ko, You-Ting Lin, Yi-Hsiu Liu, Po-Wei Liang, Jiun-Ming Kuo, Yung-Cheng Lu, Chi On Chui, Yuan-Ching Peng, Jen-Hong Chang
  • Patent number: 11545469
    Abstract: A semiconductor package including a chip stack structure, a redistribution layer (RDL) structure and conductive plugs is provided. The chip stack structure includes stacked chips. Each of the chips includes a pad. The pads on the chips are located on the same side of the chip stack structure. The RDL structure is disposed on the first sidewall of the chip stack structure and adjacent to the pads. The conductive plugs penetrate through the RDL structure. The conductive plug is connected to the corresponding pad.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: January 3, 2023
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Yi-Chung Liang
  • Publication number: 20220302082
    Abstract: A semiconductor package including a chip stack structure, a redistribution layer (RDL) structure and conductive plugs is provided. The chip stack structure includes stacked chips. Each of the chips includes a pad. The pads on the chips are located on the same side of the chip stack structure. The RDL structure is disposed on the first sidewall of the chip stack structure and adjacent to the pads. The conductive plugs penetrate through the RDL structure. The conductive plug is connected to the corresponding pad.
    Type: Application
    Filed: May 13, 2021
    Publication date: September 22, 2022
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Yi-Chung Liang
  • Publication number: 20220284966
    Abstract: A static random access memory including at least one memory cell is provided. The memory cell includes a first inverter, a second inverter, a first pass gate transistor, a second pass gate transistor, a first non-volatile memory, and a second non-volatile memory. The first inverter and the second inverter are coupled to each other. The first pass gate transistor is coupled between the first inverter and the first bit line. The second pass gate transistor is coupled between the second inverter and the second bit line. The first non-volatile memory is coupled between the first pass gate transistor and the first bit line. The second non-volatile memory is coupled between the second pass gate transistor and the second bit line.
    Type: Application
    Filed: April 13, 2021
    Publication date: September 8, 2022
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Yi-Chung Liang
  • Publication number: 20220216337
    Abstract: A manufacturing method of a semiconductor device at least includes the following steps. A substrate having a stacked structure is provided. An epitaxy process is performed to form an epitaxial layer on the substrate on two sides of the stacked structure. A recess is forming on the two sides of the stacked structure, wherein the recess penetrates through the epitaxial layer, extends into the substrate, and has a tip located in the substrate. A source/drain region is formed in the recess, wherein a material of the source/drain region comprises silicon germanium. A spacer wall material layer is formed on the substrate. A portion of the stacked structure is removed to from a gate structure. A portion of the spacer wall material layer is removed to form a spacer wall on the epitaxial layer. A semiconductor device is also provided.
    Type: Application
    Filed: March 28, 2022
    Publication date: July 7, 2022
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Yi-Chung Liang
  • Publication number: 20220181488
    Abstract: A semiconductor device including a substrate, a gate structure, a source/drain region, an epitaxial layer, and a spacer wall is provided. The substrate has an upper surface. The gate structure is arranged on the upper surface. The source/drain region is arranged on two sides of the gate structure, is partially embedded in the substrate, and has a tip located in the substrate. A material of the source/drain region includes silicon germanium. The epitaxial layer is arranged between the gate structure and the source/drain region. The spacer wall is arranged on the epitaxial layer on the two sides of the gate structure. A manufacturing method of a semiconductor device is also provided.
    Type: Application
    Filed: January 13, 2021
    Publication date: June 9, 2022
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Yi-Chung Liang
  • Patent number: 11335808
    Abstract: A semiconductor device including a substrate, a gate structure, a source/drain region, an epitaxial layer, and a spacer wall is provided. The substrate has an upper surface. The gate structure is arranged on the upper surface. The source/drain region is arranged on two sides of the gate structure, is partially embedded in the substrate, and has a tip located in the substrate. A material of the source/drain region includes silicon germanium. The epitaxial layer is arranged between the gate structure and the source/drain region. The spacer wall is arranged on the epitaxial layer on the two sides of the gate structure. A manufacturing method of a semiconductor device is also provided.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: May 17, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Yi-Chung Liang
  • Patent number: 9478552
    Abstract: A static random access memory and the manufacturing method thereof are provided. By forming the specific gate structure(s) to be concave gate structure(s) and by adjusting the ratio of the effective channel width for these gate structures, the performance of the static random access memory is enhanced.
    Type: Grant
    Filed: January 19, 2015
    Date of Patent: October 25, 2016
    Assignee: Powerchip Technology Corporation
    Inventors: Yi-Chung Liang, Chen-Hao Huang, Li-Wei Liu, Hann-Ping Hwang
  • Publication number: 20160148939
    Abstract: A static random access memory and the manufacturing method thereof are provided. By forming the specific gate structure(s) to be concave gate structure(s) and by adjusting the ratio of the effective channel width for these gate structures, the performance of the static random access memory is enhanced.
    Type: Application
    Filed: January 19, 2015
    Publication date: May 26, 2016
    Inventors: Yi-Chung Liang, Chen-Hao Huang, Li-Wei Liu, Hann-Ping Hwang