Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.

Abstract: A memory device includes a plurality of arrays coupled in parallel with each other. A first array of the plurality of arrays includes a first switch and a plurality of first memory cells that are arranged in a first column, a second switch and a plurality of second memory cells that are arranged in a second column, and at least one data line coupled to the plurality of first memory cells and the plurality of second memory cells. The second switch is configured to output a data signal from the at least one data line to a sense amplifier.

Abstract: One aspect of this description relates to a memory array. In some embodiments, the memory array includes a first memory cell coupled between a first local select line and a first local bit line, a second memory cell coupled between a second local select line and a second local bit line, a first switch coupled to a global bit line, a second switch coupled between the first local bit line and the first switch, and a third switch coupled between the second local select line and the first switch.

Abstract: An image processing method for a video processor, for generating an extrapolated frame according to a previous frame and a current frame, includes steps of: projecting a plurality of motion vectors (MVs) to the extrapolated frame subsequent to the current frame; determining whether a block of the extrapolated frame is projected by at least two of the MVs; selecting at least two candidate MVs from the MVs projected to the block when the block is projected by at least two of the MVs; calculating a blended MV which is a mixture of the at least two candidate MVs, and projecting the blended MV to the previous frame; obtaining a reference MV corresponding to position of the previous frame projected by the blended MV; and comparing the reference MV with the at least two candidate MVs, to select a final MV for the block from the at least two candidate MVs.

Abstract: A memory circuit includes a first memory cell on a first layer, a second memory cell on a second layer different from the first layer, a first select transistor on a third layer different from the first layer and the second layer, and a first bit line extending in a first direction, and being coupled to the first memory cell and the second memory cell. The memory circuit further includes a first source line extending in the first direction, being coupled to the first memory cell, the second memory cell and the first select transistor, and being separated from the first bit line in a second direction different from the first direction. memory circuit includes a second source line extending in the first direction, and being coupled to the first select transistor.

Abstract: A memory device includes a programming transistor and a reading transistor of an anti-fuse memory cell. The programming transistor includes first semiconductor nanostructures vertically spaced apart from one another, each of the first semiconductor nanostructures having a first width along a first lateral direction. The reading transistor includes second semiconductor nanostructures vertically spaced apart from one another, each of the second semiconductor nanostructures having a second width different from the first width along the second direction. The memory device also includes a first and a second gate metals. The first gate metal wraps around each of the first semiconductor nanostructures with a first gate dielectric disposed therein. The second gate metal wraps around each of the second semiconductor nanostructures with a second gate dielectric disposed therein.

Abstract: A fluid coking unit for converting a heavy oil feed to lower boiling products by thermal has a centrally-apertured annular baffle at the top of the stripping zone below the coking zone to inhibit recirculation of solid particles from the stripping zone to the coking zone. By inhibiting recirculation of the particles from the stripping zone to the coking zone, the temperatures of the two zones are effectively decoupled, enabling the coking zone to be run at a lower temperature than the stripping zone to increase the yield of liquid products.

Abstract: In various aspects, methods and systems are provided for monitoring catalyst bed levels using multiple sensors that are temporarily installed in a reactor during catalyst loading. The multiple sensors are able to take distance measurements at substantially the same time and at predetermined time intervals so as to provide a catalyst time profile. The catalyst time profile allows an operator monitor catalyst levels during and after catalyst loading. Once catalyst loading is completed, the multiple sensors are removed from the reactor.

Abstract: A fluid coking unit for converting a heavy oil feed to lower boiling products by thermal has a centrally-apertured annular baffle at the top of the stripping zone below the coking zone to inhibit recirculation of solid particles from the stripping zone to the coking zone. By inhibiting recirculation of the particles from the stripping zone to the coking zone, the temperatures of the two zones are effectively decoupled, enabling the coking zone to be run at a lower temperature than the stripping zone to increase the yield of liquid products.

Abstract: Methods, devices and processes for effectively loading catalysts into reactor vessels. In particular methods, devices and processes for effectively loading catalysts into fixed bed reactors utilizing inducted vibrational energy to improve catalyst loading performance, thereby resulting in improved flow distribution through the catalyst beds at designed operating conditions. The methods herein are particularly effectively for improving the performance of new or existing catalyst bed configurations of vertically-oriented two-phase hydroprocessing fixed bed reactors.