Patents by Inventor Yi En Huang

Yi En Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210066319
    Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a transistor, a first embedded insulating structure and a second embedded insulating structure. The transistor is formed on a substrate, and includes a gate structure, channel structures, a source electrode and a drain electrode. The channel structures penetrate through the gate structure, and are in contact with the source and drain electrodes. The first and second embedded insulating structures are disposed in the substrate, and overlapped with the source and drain electrodes. The first and second embedded insulating structures are laterally spaced apart from each other by a portion of the substrate lying under the gate structure.
    Type: Application
    Filed: March 2, 2020
    Publication date: March 4, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Sheng Chang, Chia-En Huang, Yi-Hsun Chiu, Yih Wang
  • Publication number: 20210055688
    Abstract: A three-dimensional (3D) holographic display system includes a projector that generates an image with a form of spatially varying modulation on a light beam; holographic processor that performs a holographic method on the image generated by the projector; and memory device that stores holographic data generated in a process of performing the holographic method by the holographic processor. An amplitude of a light field is adaptively replaced by the holographic processor according to significance of respective areas of the image.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Inventors: Che-Yung Shen, Shang-Hao Huang, Shang-Ting Wu, Shuo-En Lin, Yi Cheng, Yi-Pai Huang, Chi-Wen Lin
  • Publication number: 20210057408
    Abstract: A semiconductor device includes a substrate, a gate stack, and an epitaxy structure. The gate stack over the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. At least one of the top and bottom WF metal layers includes dopants, and the top WF metal layer is thicker than the bottom WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structure is over the substrate and adjacent the gate stack.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chih-Hsiung HUANG, Chung-En TSAI, Chee-Wee LIU, Kun-Wa KUOK, Yi-Hsiu HSIAO
  • Publication number: 20200357955
    Abstract: A red light emitting diode including an epitaxial stacked layer, a first and a second electrodes and a first and a second electrode pads is provided. The epitaxial stacked layer includes a first-type and a second-type semiconductor layers and a light emitting layer. A main light emitting wavelength of the light emitting layer falls in a red light range. The epitaxial stacked layer has a first side adjacent to the first semiconductor layer and a second side adjacent to the second semiconductor layer. The first and the second electrodes are respectively electrically connected to the first-type and the second-type semiconductor layers, and respectively located to the first and the second sides. The first and a second electrode pads are respectively disposed on the first and the second electrodes and respectively electrically connected to the first and the second electrodes. The first and the second electrode pads are located at the first side of the epitaxial stacked layer.
    Type: Application
    Filed: March 23, 2020
    Publication date: November 12, 2020
    Applicant: Genesis Photonics Inc.
    Inventors: Tung-Lin Chuang, Yi-Ru Huang, Yu-Chen Kuo, Chih-Ming Shen, Tsung-Syun Huang, Jing-En Huang
  • Publication number: 20200274027
    Abstract: A light emitting diode and manufacturing method thereof are provided. The light emitting diode includes a first-type semiconductor layer, a light emitting layer, a second-type semiconductor layer, a first metal layer, a first current conducting layer, a first bonding layer and a second current conducting layer. The light emitting layer is located between the first-type semiconductor layer and the second-type semiconductor layer. The first metal layer is located on and electrically connected to the first-type semiconductor layer. The first metal layer is located between the first current conducting layer and the first-type semiconductor layer. The first current conducting layer is located between the first bonding layer and the first metal layer. The first current conducting layer is connected to the first-type semiconductor layer by the first current conducting layer and the first metal layer. The first bonding layer has through holes overlapped with the first metal layer.
    Type: Application
    Filed: February 17, 2020
    Publication date: August 27, 2020
    Applicant: Genesis Photonics Inc.
    Inventors: Yi-Ru Huang, Yu-Chen Kuo, Sheng-Tsung Hsu, Chih-Ming Shen, Yao-Tang Li, Tung-Lin Chuang, Tsung-Syun Huang, Jing-En Huang
  • Patent number: 10734551
    Abstract: The invention provides an LED including a first-type semiconductor layer, an emitting layer, a second-type semiconductor layer, a first electrode, a second electrode, a Bragg reflector structure, a conductive layer and insulation patterns. The first electrode and the second electrode are located on the same side of the Bragg reflector structure. The conductive layer is disposed between the Bragg reflector structure and the second-type semiconductor layer. The insulation patterns are disposed between the conductive layer and the second-type semiconductor layer. Each insulating layer has a first surface facing toward the second-type semiconductor layer, a second surface facing away from the second-type semiconductor layer, and an inclined surface. The inclined surface connects the first surface and the second surface and is inclined with respect to the first surface and the second surface.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: August 4, 2020
    Assignee: Genesis Photonics Inc.
    Inventors: Yi-Ru Huang, Tung-Lin Chuang, Yan-Ting Lan, Sheng-Tsung Hsu, Chih-Ming Shen, Jing-En Huang, Teng-Hsien Lai, Hung-Chuan Mai, Kuan-Chieh Huang, Shao-Ying Ting, Cheng-Pin Chen, Wei-Chen Chien, Chih-Chin Cheng, Chih-Hung Tseng
  • Publication number: 20200220050
    Abstract: A light emitting diode (LED) including an epitaxial stacked layer, first and second reflective layers which are disposed at two sides of the epitaxial stacked layer, a current conducting layer and first and second electrodes and a manufacturing thereof are provided. The epitaxial stacked layer includes a first-type and a second-type semiconductor layers and an active layer. A main light emitting surface with a light transmittance >0% and ?10% is formed on one of the two reflective layers. The current conducting layer contacts the second-type semiconductor layer. The first electrode is electrically connected to the first-type semiconductor layer. The second electrode is electrically connected to the second-type semiconductor layer via the current conducting layer. A contact scope of the current conducting layer and the second-type semiconductor layer is served as a light-emitting scope overlapping the two layers, but not overlapping the two electrodes.
    Type: Application
    Filed: December 6, 2019
    Publication date: July 9, 2020
    Applicant: Genesis Photonics Inc.
    Inventors: Yi-Ru Huang, Kai-Shun Kang, Tung-Lin Chuang, Yu-Chen Kuo, Yan-Ting Lan, Chih-Ming Shen, Jing-En Huang
  • Publication number: 20200203565
    Abstract: A ?LED including an epitaxial stacked layer, a first electrode and a second electrode is provided. The epitaxial stacked layer includes a first type doped semiconductor layer, a light emitting layer and a second type doped semiconductor layer. The epitaxial stacked layer has a first mesa portion and a second mesa portion to form a first type conductive region and a second type conductive region respectively. The first electrode is disposed on the first mesa portion. The second electrode is disposed on the second mesa portion. The second electrode contacts the first type doped semiconductor layer, the light emitting layer and the second type doped semiconductor layer located at the second mesa portion. Moreover, a manufacturing method of the ?LED is also provided.
    Type: Application
    Filed: March 2, 2020
    Publication date: June 25, 2020
    Applicant: Genesis Photonics Inc.
    Inventors: Shao-Ying Ting, Yan-Ting Lan, Jing-En Huang, Yi-Ru Huang
  • Publication number: 20200194617
    Abstract: A method for manufacturing a light emitting unit is provided. A semiconductor structure including a plurality of light emitting dice separated from each other is provided. A molding compound is formed to encapsulate the light emitting dice. Each of the light emitting dice includes a light emitting element, a first electrode and a second electrode. A patterned metal layer is formed on the first electrodes and the second electrodes of the light emitting dice. A substrate is provided, where the molding compound is located between the substrate and the light emitting elements of the light emitting dice. A cutting process is performed to cut the semiconductor structure, the patterned metal layer, the molding compound and the substrate so as to define a light emitting unit with a series connection loop, a parallel connection loop or a series-parallel connection loop.
    Type: Application
    Filed: February 24, 2020
    Publication date: June 18, 2020
    Applicant: Genesis Photonics Inc.
    Inventors: Shao-Ying Ting, Kuan-Chieh Huang, Jing-En Huang, Yi-Ru Huang, Sie-Jhan Wu, Long-Lin Ke
  • Patent number: 10624809
    Abstract: The present disclosure provides a method for controlling an exoskeleton robot. The method comprises checking that a first signal is triggered by a first button, checking a tilt angle after the first signal is triggered, setting an action based on the tilt angle, and executing the action to move the exoskeleton robot. The first signal indicates to change the exoskeleton robot from a standing posture to another posture, and the tilt angle is a leaning-forward angle of a waist assembly of the exoskeleton robot relative to a line vertical to ground. The method utilizes the tilt angle to judge the intent of the user, and thus can simplify the controlling buttons to one or two buttons. Further, the controlling method also monitors the tilt angle to choose a suitable action.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: April 21, 2020
    Assignee: FREE BIONICS TAIWAN INC.
    Inventors: Yi-Jeng Tsai, Chia-En Huang, Ming-Chang Teng, Ting-Yun Wang
  • Patent number: 10629778
    Abstract: A light emitting diode structure including a substrate, a semiconductor epitaxial structure, a first insulating layer, a first reflective layer, a second reflective layer, a second insulating layer and at least one electrode. The substrate has a tilt surface. The semiconductor epitaxial structure at least exposes the tilt surface. The first insulating layer exposes a portion of the semiconductor epitaxial structure. The first reflective layer is at least partially disposed on the portion of the semiconductor epitaxial structure and electrically connected to the semiconductor epitaxial structure. The second reflective layer is disposed on the first reflective layer and the first insulating layer, and covers at least the portion of the tilt surface. The second insulating layer is disposed on the second reflective layer. The electrode is disposed on the second reflective layer and electrically connected to the first reflective layer and the semiconductor epitaxial structure.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: April 21, 2020
    Assignee: Genesis Photonics Inc.
    Inventors: Yi-Ru Huang, Yu-Yun Lo, Chih-Ling Wu, Jing-En Huang, Shao-Ying Ting
  • Publication number: 20200107041
    Abstract: A frame rate up-conversion (FRC) apparatus and an operation method thereof are provided. A motion vector (MV) generation circuit provides an MV of a current pixel of an interpolation frame. According to the MV, a data fetch circuit fetches first original data of a first pixel in a first original frame and second original data of a second pixel in a second original frame. According to a position of the first pixel in the first original frame and a position of the second pixel in the second original frame, a boundary processing circuit processes the first original data and the second original data to generate first processed data and second processed data. An interpolation frame generating circuit generates pixel data of the current pixel of the interpolation frame according to the first processed data and the second processed data.
    Type: Application
    Filed: October 1, 2018
    Publication date: April 2, 2020
    Applicant: Novatek Microelectronics Corp.
    Inventors: Yi-Hung Huang, Hsiao-En Chang, Jia-Lin Liao
  • Patent number: 10608144
    Abstract: Provided is a light emitting diode (LED) mounted on a carrier substrate and including a semiconductor epitaxial structure and at least one electrode pad structure. The semiconductor epitaxial structure is electrically connected to the carrier substrate. The electrode pad structure includes a eutectic layer, a barrier layer and a ductility layer. The eutectic layer is adapted for eutectic bonding to the carrier substrate. The barrier layer is between the eutectic layer and the semiconductor epitaxial structure. The barrier layer blocks the diffusion of the material of the eutectic layer in the eutectic bonding process. The ductility layer is between the eutectic layer and the semiconductor epitaxial structure. The ductility layer reduces the stress on the LED produced by thermal expansion and contraction of the substrate during the eutectic bonding process, so as to prevent the electrode pad structure from cracking, and maintain the quality of the LED.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: March 31, 2020
    Assignee: Genesis Photonics Inc.
    Inventors: Yi-Ru Huang, Tung-Lin Chuang, Chih-Ming Shen, Sheng-Tsung Hsu, Kuan-Chieh Huang, Jing-En Huang, Shao-Ying Ting
  • Patent number: 10602177
    Abstract: A frame rate up-conversion (FRC) apparatus and an operation method thereof are provided. A motion vector (MV) generation circuit provides an MV of a current pixel of an interpolation frame. According to the MV, a data fetch circuit fetches first original data of a first pixel in a first original frame and second original data of a second pixel in a second original frame. According to a position of the first pixel in the first original frame and a position of the second pixel in the second original frame, a boundary processing circuit processes the first original data and the second original data to generate first processed data and second processed data. An interpolation frame generating circuit generates pixel data of the current pixel of the interpolation frame according to the first processed data and the second processed data.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: March 24, 2020
    Assignee: Novatek Microelectronics Corp.
    Inventors: Yi-Hung Huang, Hsiao-En Chang, Jia-Lin Liao
  • Publication number: 20200075821
    Abstract: A light emitting diode chip including an epitaxy stacked layer, first and second electrodes and a first reflective layer is provided. The epitaxy stacked layer includes first-type and second-type semiconductor layers and a light-emitting layer. The first and second electrodes are respectively electrically connected to the first-type and second-type semiconductor layers. An orthogonal projection of the light-emitting layer on the first-type semiconductor layer is misaligned with an orthogonal projection of the first electrode on the first-type semiconductor layer. The first reflective layer is disposed on the epitaxy stacked layer, the first and second electrodes. An orthogonal projection of the first reflective layer on the second-type semiconductor layer is misaligned with an orthogonal projection of the second electrode on the second-type semiconductor layer. Furthermore, a light emitting diode device is also provided.
    Type: Application
    Filed: August 5, 2019
    Publication date: March 5, 2020
    Applicant: Genesis Photonics Inc.
    Inventors: Tung-Lin Chuang, Yi-Ru Huang, Yu-Chen Kuo, Yan-Ting Lan, Chih-Ming Shen, Jing-En Huang
  • Patent number: 10580934
    Abstract: A ?LED including an epitaxial stacked layer, a first electrode and a second electrode is provided. The epitaxial stacked layer includes a first type doped semiconductor layer, a light emitting layer and a second type doped semiconductor layer. The epitaxial stacked layer has a first mesa portion and a second mesa portion to form a first type conductive region and a second type conductive region respectively. The first electrode is disposed on the first mesa portion. The second electrode is disposed on the second mesa portion. The second electrode contacts the first type doped semiconductor layer, the light emitting layer and the second type doped semiconductor layer located at the second mesa portion. Moreover, a manufacturing method of the ?LED is also provided.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: March 3, 2020
    Assignee: Genesis Photonics Inc.
    Inventors: Shao-Ying Ting, Yan-Ting Lan, Jing-En Huang, Yi-Ru Huang
  • Patent number: 10573779
    Abstract: A method for manufacturing a light emitting unit is provided. A semiconductor structure including a plurality of light emitting dice separated from each other is provided. A molding compound is formed to encapsulate the light emitting dice. Each of the light emitting dice includes a light emitting element, a first electrode and a second electrode. A patterned metal layer is formed on the first electrodes and the second electrodes of the light emitting dice. A substrate is provided, where the molding compound is located between the substrate and the light emitting elements of the light emitting dice. A cutting process is performed to cut the semiconductor structure, the patterned metal layer, the molding compound and the substrate so as to define a light emitting unit with a series connection loop, a parallel connection loop or a series-parallel connection loop.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: February 25, 2020
    Assignee: Genesis Photonics Inc.
    Inventors: Shao-Ying Ting, Kuan-Chieh Huang, Jing-En Huang, Yi-Ru Huang, Sie-Jhan Wu, Long-Lin Ke
  • Publication number: 20200052159
    Abstract: The invention provides an LED including a first-type semiconductor layer, an emitting layer, a second-type semiconductor layer, a first electrode, a second electrode, a Bragg reflector structure, a conductive layer and insulation patterns. The first electrode and the second electrode are located on the same side of the Bragg reflector structure. The conductive layer is disposed between the Bragg reflector structure and the second-type semiconductor layer. The insulation patterns are disposed between the conductive layer and the second-type semiconductor layer. Each insulating layer has a first surface facing toward the second-type semiconductor layer, a second surface facing away from the second-type semiconductor layer, and an inclined surface. The inclined surface connects the first surface and the second surface and is inclined with respect to the first surface and the second surface.
    Type: Application
    Filed: October 21, 2019
    Publication date: February 13, 2020
    Applicant: Genesis Photonics Inc.
    Inventors: Yi-Ru Huang, Tung-Lin Chuang, Yan-Ting Lan, Sheng-Tsung Hsu, Chih-Ming Shen, Jing-En Huang, Teng-Hsien Lai, Hung-Chuan Mai, Kuan-Chieh Huang, Shao-Ying Ting, Cheng-Pin Chen, Wei-Chen Chien, Chih-Chin Cheng, Chih-Hung Tseng
  • Publication number: 20190320659
    Abstract: The present invention relates to a plant growth regulator of elevating anti-stress ability and use thereof. The plant growth regulator, which is consisted of Lactobacillus fermenting culture solution, has excellent thermostability and safety without any side effect, significantly elevating ability against biotic and abiotic stresses. Therefore, the Lactobacillus fermenting culture solution can be applied as the plant growth regulator or a use in preparation of a composition for elevating anti-stress ability of a plant.
    Type: Application
    Filed: March 25, 2019
    Publication date: October 24, 2019
    Inventors: Yi-Hsing Chen, Wan-Hua Tsai, Tsuei-Yin Huang, Hsiang-En Huang, Yu-Jen Hsu
  • Patent number: D872701
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: January 14, 2020
    Assignee: GENESIS PHOTONICS INC.
    Inventors: Shao-Ying Ting, Yan-Ting Lan, Jing-En Huang, Yi-Ru Huang