Patents by Inventor Yi-Fan Chen
Yi-Fan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190171689Abstract: A search computing system receives an interaction history for one or more respective users describing interactions with one or more items and generates a co-interaction matrix, each value in the co-interaction matrix representing a number of common users determined to have had the interaction with an item of a corresponding row and an item of the corresponding column of the co-interaction matrix where the value is located. The search computing system generates an embeddings matrix comprising an item embedding value for each of the one or more items by applying matrix factorization to the co-interaction matrix and determines, in response to a search query of a particular user, a user embedding value for the searching user based on the interaction history for the searching user. The search computing system determines a similarity between each search result and user interaction history by comparing the user embedding value against each of the item embedding values.Type: ApplicationFiled: December 5, 2018Publication date: June 6, 2019Inventors: Ahmed Kachkach, Yi-fan Chen, Karthik Lakshmanan, Sally Goldman, Puneet Chopra, Radhika Malpani, Jeremy Shute, Berna Erol
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Publication number: 20190103277Abstract: Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.Type: ApplicationFiled: April 13, 2018Publication date: April 4, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hongfa LUAN, Huicheng CHANG, Cheng-Po CHAU, Wen-Yu KU, Yi-Fan CHEN, Chun-Yen PENG
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Patent number: 10249530Abstract: A method of forming a semiconductor device includes depositing a flowable dielectric layer on a substrate and annealing the flowable dielectric layer. The method further includes performing a high temperature (HT) doping process on the flowable dielectric layer. The HT doping process may include implanting dopant ions into the flowable dielectric layer and heating the substrate during the implanting of the dopant ions. The heating of the substrate may include heating a substrate holder upon which the substrate is disposed and maintaining the substrate at a temperature above 100° C. An example benefit reduced the wet etch rate (WER) of the flowable dielectric layer.Type: GrantFiled: March 29, 2017Date of Patent: April 2, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsan-Chun Wang, De-Wei Yu, Ziwei Fang, Yi-Fan Chen
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Publication number: 20190012719Abstract: Implementations include systems and methods for scoring candidates for set recommendation problems. An example method includes repeating, for each code in code arrays for items in a set of items, determining a most common value for the code. In some implementations, the method includes determining that the most common value occurs with a frequency that meets an occurrence threshold and adding the code and the most common value to set-inclusion criteria. In other implementations, the method includes determining a value for the code from a code array for a seed item and adding the code and the most common value to set-inclusion criteria when the value for the code from the code array for the seed item matches the most common value. The method may also include evaluating a similarity with a candidate item based on the set-inclusion criteria and basing a recommendation regarding the candidate item on the similarity.Type: ApplicationFiled: September 12, 2018Publication date: January 10, 2019Inventors: John Roberts Anderson, Ryan Michael Rifkin, Jay Yagnik, Rasmus Larsen, Sarvjeet Singh, Yi-fan Chen, Anandsudhakar Kesari
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Patent number: 10115146Abstract: Implementations include systems and methods for scoring candidates for set recommendation problems. An example method includes repeating, for each code in code arrays for items in a set of items, determining a most common value for the code. In some implementations, the method includes determining that the most common value occurs with a frequency that meets an occurrence threshold and adding the code and the most common value to set-inclusion criteria. In other implementations, the method includes determining a value for the code from a code array for a seed item and adding the code and the most common value to set-inclusion criteria when the value for the code from the code array for the seed item matches the most common value. The method may also include evaluating a similarity with a candidate item based on the set-inclusion criteria and basing a recommendation regarding the candidate item on the similarity.Type: GrantFiled: April 16, 2015Date of Patent: October 30, 2018Assignee: GOOGLE LLCInventors: John Roberts Anderson, Ryan Michael Rifkin, Jay Yagnik, Rasmus Larsen, Sarvjeet Singh, Yi-Fan Chen, Anandsudhakar Kesari
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Patent number: 10008292Abstract: A memory auto repairing circuit including: a decoding circuit, a latch enable circuit and a first latch circuit, wherein the decoding circuit is arranged to compare a first input address with a plurality of fail addresses to generate a control signal; the latch enable circuit is arranged to selectively generate a first enable signal at least according to the control signal; and the first latch circuit is arranged to receive the first input address, and store the first input address when the first enable signal is received by the first latch circuit; wherein when the control signal indicates that the first input address is identical to one of the plurality of fail addresses, the enable signal is prevented from being transmitted from the latch enable circuit to the first latch circuit.Type: GrantFiled: December 14, 2016Date of Patent: June 26, 2018Assignee: Elite Semiconductor Memory Technology Inc.Inventors: Tse-Hua Yao, Yi-Fan Chen
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Publication number: 20180166153Abstract: a memory auto repairing circuit including: a decoding circuit, a latch enable circuit and a first latch circuit, wherein the decoding circuit is arranged to compare a first input address with a plurality of fail addresses to generate a control signal; the latch enable circuit is arranged to selectively generate a first enable signal at least according to the control signal; and the first latch circuit is arranged to receive the first input address, and store the first input address when the first enable signal is received by the first latch circuit; wherein when the control signal indicates that the first input address is identical to one of the plurality of fail addresses, the enable signal is prevented from being transmitted from the latch enable circuit to the first latch circuit.Type: ApplicationFiled: December 14, 2016Publication date: June 14, 2018Inventors: Tse-Hua Yao, Yi-Fan Chen
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Patent number: 9995998Abstract: A method includes receiving a layout of an integrated circuit (IC) device, the layout having an outer boundary and an inner boundary thereby defining a first region between the outer boundary and the inner boundary and placing a first plurality of dummy patterns in the first region, wherein the first plurality of dummy patterns is lithographically printable. The method further includes performing an Optical Proximity Correction (OPC) process, the first plurality of dummy patterns being position within the first region in such a way that prevents sub-resolution assist features from being inserted into the first region by the OPC process.Type: GrantFiled: June 21, 2016Date of Patent: June 12, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Fan Chen, Tung-Heng Hsieh, Chin-Shan Hou, Yu-Bey Wu
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Publication number: 20170207117Abstract: A method of forming a semiconductor device includes depositing a flowable dielectric layer on a substrate and annealing the flowable dielectric layer. The method further includes performing a high temperature (HT) doping process on the flowable dielectric layer. The FIT doping process may include implanting dopant ions into the flowable dielectric layer and heating the substrate during the implanting of the dopant ions. The heating of the substrate may include heating a substrate holder upon which the substrate is disposed and maintaining the substrate at a temperature above 100° C. An example benefit reduced the wet etch rate (WER) of the flowable dielectric layer.Type: ApplicationFiled: March 29, 2017Publication date: July 20, 2017Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsan-Chun WANG, De-Wei YU, Ziwei FANG, Yi-Fan CHEN
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Publication number: 20170176864Abstract: Embodiments of the present invention provide methods for optimizing a lithographic projection apparatus including optimizing projection optics therein. The current embodiments include several flows including optimizing a source, a mask, and the projection optics and various sequential and iterative optimization steps combining any of the projection optics, mask and source. The projection optics is sometimes broadly referred to as “lens”, and therefore the optimization process may be termed source mask lens optimization (SMLO). SMLO may be desirable over existing source mask optimization process (SMO) or other optimization processes that do not include projection optics optimization, partially because including the projection optics in the optimization may lead to a larger process window by introducing a plurality of adjustable characteristics of the projection optics.Type: ApplicationFiled: March 6, 2017Publication date: June 22, 2017Applicant: ASML Netherlands B.V.Inventors: Duan-Fu HSU, Luoqi Chen, Hanying Feng, Rafael C. Howell, Xinjian Zhou, Yi-Fan Chen
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Patent number: 9634141Abstract: A method of forming a semiconductor device includes depositing a flowable dielectric layer on a substrate and annealing the flowable dielectric layer. The method further includes performing a high temperature (HT) doping process on the flowable dielectric layer. The HT doping process may include implanting dopant ions into the flowable dielectric layer and heating the substrate during the implanting of the dopant ions. The heating of the substrate may include heating a substrate holder upon which the substrate is disposed and maintaining the substrate at a temperature above 100° C. An example benefit reduced the wet etch rate (WER) of the flowable dielectric layer.Type: GrantFiled: October 14, 2015Date of Patent: April 25, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsan-Chun Wang, De-Wei Yu, Ziwei Fang, Yi-Fan Chen
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Publication number: 20170110577Abstract: A method of forming a semiconductor device includes depositing a flowable dielectric layer on a substrate and annealing the flowable dielectric layer. The method further includes performing a high temperature (HT) doping process on the flowable dielectric layer. The HT doping process may include implanting dopant ions into the flowable dielectric layer and heating the substrate during the implanting of the dopant ions. The heating of the substrate may include heating a substrate holder upon which the substrate is disposed and maintaining the substrate at a temperature above 100° C. An example benefit reduced the wet etch rate (WER) of the flowable dielectric layer.Type: ApplicationFiled: October 14, 2015Publication date: April 20, 2017Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsan-Chun WANG, De-Wei YU, Ziwei FANG, Yi-Fan CHEN
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Patent number: 9588438Abstract: Embodiments of the present invention provide methods for optimizing a lithographic projection apparatus including optimizing projection optics therein. The current embodiments include several flows including optimizing a source, a mask, and the projection optics and various sequential and iterative optimization steps combining any of the projection optics, mask and source. The projection optics is sometimes broadly referred to as “lens”, and therefore the optimization process may be termed source mask lens optimization (SMLO). SMLO may be desirable over existing source mask optimization process (SMO) or other optimization processes that do not include projection optics optimization, partially because including the projection optics in the optimization may lead to a larger process window by introducing a plurality of adjustable characteristics of the projection optics.Type: GrantFiled: November 9, 2011Date of Patent: March 7, 2017Assignee: ASML NETHERLANDS B.V.Inventors: Duan-Fu Hsu, Luoqi Chen, Hanying Feng, Rafael C. Howell, Xinjian Zhou, Yi-Fan Chen
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Publication number: 20170030944Abstract: Wireless piezoelectric accelerometers and systems are provided. A wireless piezoelectric accelerometer may comprise a piezoelectric sensing element configured to sense mechanical acceleration and produce an electrical charge signal in response of the sensed mechanical acceleration, a signal processing module (SPM) configured to convert the electrical charge signal into a voltage signal, and process and digitize the voltage signal, and a wireless module configured to modulate and transmit the digitized voltage signal as wireless signals. The piezoelectric sensing element, the SPM and the wireless module are packaged in a casing. The casing comprises a metallic shielding chamber configured to enclose the piezoelectric sensing element. The casing further comprises a non-metallic portion located in relative to the wireless module to allow transmission of the wireless signals. Corresponding wireless piezoelectric accelerometer systems are also provided.Type: ApplicationFiled: April 10, 2015Publication date: February 2, 2017Inventors: Kui Yao, Zhiyuan Shen, Chin Yaw Tan, Yi Fan Chen, Lei Zhang
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Publication number: 20160370698Abstract: A method includes receiving a layout of an integrated circuit (IC) device, the layout having an outer boundary and an inner boundary thereby defining a first region between the outer boundary and the inner boundary and placing a first plurality of dummy patterns in the first region, wherein the first plurality of dummy patterns is lithographically printable. The method further includes performing an Optical Proximity Correction (OPC) process, the first plurality of dummy patterns being position within the first region in such a way that prevents sub-resolution assist features from being inserted into the first region by the OPC process.Type: ApplicationFiled: June 21, 2016Publication date: December 22, 2016Inventors: Yi-Fan Chen, Tung-Heng Hsieh, Chin-Shan Hou, Yu-Bey Wu
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Publication number: 20160313316Abstract: An influenza detector for detecting a targeted influenza virus and a surface acoustic wave (SAW) sensor for Influenza A virus detection in liquid are provided. The influenza detector includes a liquid environment, the surface acoustic wave (SAW) sensor and an influenza specific binding agent such as an antibody. The agent is immobilized on a surface of the SAW sensor for selectively capturing an analyte for the targeted influenza virus. The SAW sensor is in contact with the liquid environment and includes a substrate comprising a piezo-electric material for producing a surface acoustic wave signal in response to an applied electric field and an insulative layer formed on top of the substrate and having a functionalized surface formed thereon for selectively immobilizing the influenza specific binding agent, the functionalized surface being in contact with the liquid environment.Type: ApplicationFiled: December 10, 2014Publication date: October 27, 2016Inventors: Kui YAO, Chin Yaw TAN, Ying JIANG, Yi Fan CHEN, Sze Yu TAN, Lei ZHANG
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Patent number: 9423295Abstract: According to one aspect of the invention, there is provided a photo-sensor comprising: an optically transparent substrate; an electrode pair; and a photoactive film with electrical polarization located between the optically transparent substrate and the electrode pair, wherein the optically transparent substrate is configured to transmit incident radiation received by the optically transparent substrate to the photoactive film and wherein the electrode pair is configured to receive charge carriers generated by the photoactive film in response to the transmitted incident radiation.Type: GrantFiled: April 24, 2014Date of Patent: August 23, 2016Assignee: Agency for Science, Technology and ResearchInventors: Szu Cheng Lai, Kui Yao, Yi Fan Chen, Yee Fun Lim
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Patent number: 9377680Abstract: Provided is an integrated circuit (IC) testline layout. The layout has a device boundary and a main pattern boundary inside the device boundary. The layout includes at least one main pattern inside the main pattern boundary. The layout further includes a plurality of dummy patterns in a region that is between the main pattern boundary and the device boundary. The plurality of dummy patterns is printable in a photolithography process and is arranged in a ring with a uniform spacing between two adjacent dummy patterns.Type: GrantFiled: November 15, 2013Date of Patent: June 28, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Fan Chen, Tung-Heng Hsieh, Chin-Shan Hou, Yu-Bey Wu
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Patent number: 9373378Abstract: The semiconductor device incorporates a selected sub word line driver and a first voltage switching circuit. The selected sub word line driver has an input node connected to a selected main word line, an output node connected to a selected sub word line, a reference node supplied with a common reference voltage, and a power node. The first voltage switching circuit selectively supplies a first power voltage, a second power voltage, or the common reference voltage to the power node of the selected sub word line driver. In an active mode, the first voltage switching circuit supplies the first power voltage to pull the selected sub word line to a logic high level. In a precharge mode, the first voltage switching circuit supplies the common reference voltage and then supplies the second power voltage, thereby pulling the selected sub word line to a logic low level. A voltage level of the second power supply node is lower than a voltage level of the first power voltage and higher than the common reference voltage.Type: GrantFiled: March 26, 2015Date of Patent: June 21, 2016Assignee: Elite Semiconductor Memory Technology Inc.Inventor: Yi-Fan Chen
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Patent number: 9164623Abstract: A portable device and a key hit area adjustment method are provided. The portable device includes a touch screen and a processor coupled with the touch screen. The touch screen is configured to display an input method editor comprising a plurality of virtual keys. The processor is configured to detect an input event triggered via the input method editor and adjust key hit areas of the virtual keys in response to the input event. The key hit area adjustment method is applied to the portable device to implement the aforesaid operations.Type: GrantFiled: February 28, 2013Date of Patent: October 20, 2015Assignee: HTC CORPORATIONInventors: Huan-Chih Tseng, Kuan-Wei Li, Yi-Fan Chen, Hsueh-Chun Chen