Patents by Inventor Yi-Hsien Chang

Yi-Hsien Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170203961
    Abstract: In the present disclosure a semiconductor device comprises a plate including a plurality of apertures. The semiconductor device also comprises a membrane disposed opposite to the plate and including a plurality of corrugations, a dielectric surrounding and covering an edge of the membrane, and a substrate. The semiconductor device further includes a metallic conductor comprising a first portion extending through the dielectric, and a second portion over the substrate, where the second portion is bonded with the first portion.
    Type: Application
    Filed: January 19, 2016
    Publication date: July 20, 2017
    Inventors: YI-HSIEN CHANG, CHUN-REN CHENG
  • Patent number: 9709525
    Abstract: The present disclosure provides a bio-field effect transistor (BioFET) device and methods of fabricating a BioFET and a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a gate structure disposed on a first surface of a substrate and an interface layer formed on a second surface of the substrate. The substrate is thinned from the second surface to expose a channel region before forming the interface layer.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: July 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Shao Liu, Chun-Ren Cheng, Ching-Ray Chen, Yi-Hsien Chang, Fei-Lung Lai, Chun-Wen Cheng
  • Patent number: 9616617
    Abstract: The present disclosure provides a biochip and methods of fabricating. The biochip includes a fluidic part and a sensing part bonded together using a polymer. The fluidic part has microfluidic channel pattern on one side and fluidic inlet and fluidic outlet on the other side that are fluidly connected to the microfluidic channel pattern. The fluidic inlet and fluidic outlet are formed by laser drilling after protecting the microfluidic channel pattern with a sacrificial protective layer. The polymer bonding is performed at low temperature without damaging patterned surface chemistry on a sensing surface of the sensing part.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: April 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Cheng Shen, Yi-Shao Liu, Yi-Hsien Chang, Chun-Ren Cheng
  • Publication number: 20170067890
    Abstract: Dual-gate ion-sensitive field effect transistor (ISFET) and methods implementing the dual-gate ISFETs for disease diagnostics are disclosed herein. An exemplary method includes providing a biological sample to a dual-gate ISFET. The dual-gate ISFET includes a fluidic gate structure and a gate structure, where the fluidic gate structure and the gate structure are disposed over opposite surfaces of a device substrate. The method further includes generating enzymatic reactions from enzyme-modified detection mechanisms. The enzyme-modified detection mechanisms release ions into an electrolyte solution of the fluidic gate structure. The method further includes biasing the fluidic gate structure and the gate structure to generate an electrical signal as a sensing layer of the fluidic gate structure reacts with the ions. The electrical signal indicates an ion concentration in the electrolyte solution that correlates with a presence or a quantity of target analytes in the biological sample.
    Type: Application
    Filed: November 18, 2016
    Publication date: March 9, 2017
    Inventors: Ching-Hui Lin, Chun-Ren Cheng, Yi-Hsien Chang, Shih-Fen Huang
  • Publication number: 20170029268
    Abstract: A semiconductor structure includes a first device and a second device. The first device includes a plate including a plurality of apertures; a membrane disposed opposite to the plate and including a plurality of corrugations, and a conductive plug extending through the plate and the membrane. The second device includes a substrate and a bond pad disposed over the substrate, wherein the conductive plug is bonded with the bond pad to integrate the first device with the second device, and the plate includes a semiconductive member and a tensile member, and the semiconductive member is disposed within the tensile member.
    Type: Application
    Filed: July 31, 2015
    Publication date: February 2, 2017
    Inventors: YI-HSIEN CHANG, CHUN-REN CHENG, WEI-CHENG SHEN, WEN-CHIEN CHEN
  • Publication number: 20170016851
    Abstract: The present disclosure relates to an integrated chip having an integrated bio-sensor with horizontal and vertical sensing surfaces. In some embodiments, the integrated chip has a sensing device disposed within a substrate, and a lower metal wire over the substrate and electrically coupled to the sensing device. First and second metal vias are arranged on the lower metal wire at locations set back from sidewalls of the lower metal wire, and first and second upper metal wires respectively cover top surfaces of the first and second metal vias. A dielectric structure surrounds the lower metal wire, the first and second metal vias, and the first and second upper metal wires. A sensing well has sensing surfaces that extend along an upper surface of the lower metal wire and along sidewalls of the first and second metal vias and the first and second upper metal wires.
    Type: Application
    Filed: September 27, 2016
    Publication date: January 19, 2017
    Inventors: Chun-Wen Cheng, Fei-Lung Lai, Chia-Hua Chu, Yi-Hsien Chang, Hsin-Chieh Huang
  • Publication number: 20160362292
    Abstract: A semiconductor structure includes a first device and a second device. The first device includes a plate including a plurality of apertures, a membrane disposed opposite to the plate and including a plurality of corrugations facing the plurality of apertures, and a conductive plug extending from the plate through the membrane. The second device includes a substrate and a bond pad disposed over the substrate, wherein the conductive plug is bonded with the bond pad to integrate the first device with the second device, and the plate is an epitaxial (EPI) silicon layer or a silicon-on-insulator (SOI) substrate.
    Type: Application
    Filed: June 15, 2015
    Publication date: December 15, 2016
    Inventors: YI-HSIEN CHANG, CHUN-WEN CHENG, CHUN-REN CHENG, SHIH-WEI LIN, WEI-CHENG SHEN
  • Publication number: 20160341656
    Abstract: The present disclosure relates to an integrated chip having an integrated optical bio-sensor, and an associated method of fabrication. In some embodiments, the integrated optical bio-sensor has a sensing device arranged within a semiconductor substrate. An optical waveguide structure is located over a first side of the semiconductor substrate at a position over the sensing device. A dielectric structure is disposed onto the optical waveguide structure at a position that separates the optical waveguide structure from a sample retention area configured to receive a sample solution.
    Type: Application
    Filed: May 22, 2015
    Publication date: November 24, 2016
    Inventors: Yi-Shao Liu, Emerson Cheng, Yi-Hsien Chang, Chun-Ren Cheng, Ching-Ray Chen, Alex Kalnitsky, Allen Timothy Chang
  • Patent number: 9493347
    Abstract: A method of forming a semiconductor device includes depositing a light reflecting layer over a substrate. The method also includes forming a protection layer over the light reflecting layer. The method further includes forming an anti-reflective coating (ARC) layer over the protection layer. The method additionally includes forming an opening in the ARC layer, the protection layer and the light reflecting layer exposing the substrate. The method also includes removing the ARC layer in a wet solution comprising H2O2, the ARC layer being exposed to the H2O2 at a flow rate greater than about 10 standard cubic centimeters per minute (sccm).
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: November 15, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Hsien Chang, Chun-Ren Cheng, Yi-Shao Liu, Allen Timothy Chang, Ching-Ray Chen, Yeh-Tseng Li, Wen-Hsiang Lin
  • Patent number: 9493346
    Abstract: An integrated circuit (IC) structure is provided. The IC structure includes an IC substrate including active devices which are coupled together through a conductive interconnect structure arranged thereover. The conductive interconnect structure includes a series of horizontal conductive layers and dielectric regions arranged between neighboring horizontal conductive layers. The conductive interconnect structure includes an uppermost conductive horizontal region with a planar top surface region. A MEMS substrate is arranged over the IC substrate and includes a flexible or moveable structure that flexes or moves commensurate with a force applied to the flexible or moveable structure. The active devices of the IC substrate are arranged to establish analysis circuitry to facilitate electrical measurement of a capacitance between the uppermost conductive horizontal region and the flexible or moveable structure.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: November 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Cheng Shen, Yi-Hsien Chang, Yi Heng Tsai, Tzu-Heng Wu, Chun-Ren Cheng, Chun-Wen Cheng
  • Patent number: 9488615
    Abstract: The present disclosure relates to an integrated chip having an integrated bio-sensor having horizontal and vertical sensing surfaces. In some embodiments, the integrated chip has a sensing device disposed within a semiconductor substrate. A back-end-of the line (BEOL) metallization stack with a plurality of metal interconnect layers electrically coupled to the sensing device is arranged within an inter-level dielectric (ILD) layer overlying the semiconductor substrate. A sensing well is located within a top surface of the ILD layer. The sensing well has a horizontal sensing surface extending along a top surface of a first one of the plurality of metal interconnect layers and a vertical sensing surface extending along a sidewall of a second one of the plurality of metal interconnect layers overlying the first one of the plurality of metal interconnect layers. The use of both horizontal and vertical sensing surfaces enables more accurate sensing.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: November 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Wen Cheng, Fei-Lung Lai, Chia-Hua Chu, Yi-Hsien Chang, Hsin-Chieh Huang
  • Publication number: 20160281158
    Abstract: An integrated semiconductor device for manipulating and processing bio-entity samples and methods are described. The device includes a lower substrate, at least one optical signal conduit disposed on the lower substrate, at least one cap bonding pad disposed on the lower substrate, a cap configured to form a capped area, and disposed on the at least one cap bonding pad, a fluidic channel, wherein a first side of the fluidic channel is formed on the lower substrate and a second side of the fluidic channel is formed on the cap, a photosensor array coupled to sensor control circuitry, and logic circuitry coupled to the fluidic control circuitry, and the sensor control circuitry.
    Type: Application
    Filed: June 10, 2016
    Publication date: September 29, 2016
    Inventors: Allen Timothy Chang, Yi-Hsien Chang, Chun-Ren Cheng
  • Patent number: 9446945
    Abstract: A three-dimensional (3D) integrated circuit (IC) includes a first IC and a second IC. The first IC includes a MEMS device and a first bonding structure. The second IC includes a second bonding structure. The first and second bonding structures are bonded together to couple the first IC to the second IC. A conformal barrier layer is disposed over a surface of the second IC nearest the first IC. An etch isolation structure is arranged beneath the surface of the second IC and encloses a sacrificial region which is arranged on either side of the second bonding structure and which is arranged in the second IC.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: September 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Heng Tsai, Yi-Hsien Chang, Chun-Ren Cheng, Chun-Wen Cheng, Tzu-Heng Wu, Wei-Cheng Shen
  • Patent number: 9449867
    Abstract: The present disclosure relates to an integrated microsystem with a protection barrier structure, and an associated method. In some embodiments, the integrated microsystem comprises a first die having a plurality of CMOS devices disposed thereon, a second die having a plurality of MEMS devices disposed thereon and a vapor hydrofluoric acid (vHF) etch barrier structure disposed between the first die and the second die. The second die is bonded to the first die at a bond interface region. The vHF etch barrier structure comprises a vHF barrier layer over an upper surface of the first die, and a stress reduction layer arranged between the vHF etch barrier layer and the upper surface of the first die.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: September 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzu-Heng Wu, Yi-Hsien Chang, Kai-Chih Liang, Yi Heng Tsai, Wei-Cheng Shen, Chun-Ren Cheng, Chun-Wen Cheng, Han-Chin Chiu
  • Publication number: 20160264399
    Abstract: A MEMS transducer includes a first substrate and a second substrate facing the first substrate. The first substrate includes a piezoelectric diaphragm and a conductive contact structure. The conductive contact structure is electrically connected to the piezoelectric diaphragm, and protrudes beyond a principal surface of the first substrate. The second substrate includes a conductive receiving feature and an active device. The conductive receiving feature is aligned with and further bonded to the conductive contact structure. The active device is electrically connected to the piezoelectric diaphragm through the conductive receiving feature and the conductive contact structure.
    Type: Application
    Filed: March 13, 2015
    Publication date: September 15, 2016
    Inventors: Chun-Ren CHENG, Richard YEN, Yi-Hsien CHANG, Wei-Cheng SHEN
  • Patent number: 9417209
    Abstract: The present disclosure provides a biological field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET includes a microwells having a sensing layer, a top metal stack under the sensing layer, and a multi-layer interconnect (MLI) under the top metal stack. The top metal stack includes a top metal and a protective layer over and peripherally surrounding the top metal.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: August 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Cheng Shen, Yi-Hsien Chang, Shih-Wei Lin, Chun-Ren Cheng
  • Publication number: 20160207756
    Abstract: A substrate structure for a micro electro mechanical system (MEMS) device, a semiconductor structure and a method for fabricating the same are provided. In various embodiments, the substrate structure for the MEMS device includes a substrate, the MEMS device, and an anti-stiction layer. The MEMS device is over the substrate. The anti-stiction layer is on a surface of the MEMS device, and includes amorphous carbon, polytetrafluoroethene, hafnium oxide, tantalum oxide, zirconium oxide, or a combination thereof.
    Type: Application
    Filed: January 16, 2015
    Publication date: July 21, 2016
    Inventors: Yi-Hsien CHANG, Tzu-Heng WU, Chun-Ren CHENG, Shih-Wei LIN, Jung-Kuo TU
  • Publication number: 20160178568
    Abstract: The present disclosure relates to an integrated chip having an integrated bio-sensor having horizontal and vertical sensing surfaces. In some embodiments, the integrated chip has a sensing device disposed within a semiconductor substrate. A back-end-of the line (BEOL) metallization stack with a plurality of metal interconnect layers electrically coupled to the sensing device is arranged within an inter-level dielectric (ILD) layer overlying the semiconductor substrate. A sensing well is located within a top surface of the ILD layer. The sensing well has a horizontal sensing surface extending along a top surface of a first one of the plurality of metal interconnect layers and a vertical sensing surface extending along a sidewall of a second one of the plurality of metal interconnect layers overlying the first one of the plurality of metal interconnect layers. The use of both horizontal and vertical sensing surfaces enables more accurate sensing.
    Type: Application
    Filed: December 17, 2014
    Publication date: June 23, 2016
    Inventors: Chun-Wen Cheng, Fei-Lung Lai, Chia-Hua Chu, Yi-Hsien Chang, Hsin-Chieh Huang
  • Patent number: 9366647
    Abstract: An integrated semiconductor device for manipulating and processing bio-entity samples and methods are described. The device includes a lower substrate, at least one optical signal conduit disposed on the lower substrate, at least one cap bonding pad disposed on the lower substrate, a cap configured to form a capped area, and disposed on the at least one cap bonding pad, a microfluidic channel, wherein a first side of the microfluidic channel is formed on the lower substrate and a second side of the microfluidic channel is formed on the cap, a photosensor array coupled to sensor control circuitry, and logic circuitry coupled to the fluidic control circuitry, and the sensor control circuitry.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: June 14, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Allen Timothy Chang, Yi-Hsien Chang, Chun-Ren Cheng
  • Publication number: 20160145095
    Abstract: A three-dimensional (3D) integrated circuit (IC) includes a first IC and a second IC. The first IC includes a MEMS device and a first bonding structure. The second IC includes a second bonding structure. The first and second bonding structures are bonded together to couple the first IC to the second IC. A conformal barrier layer is disposed over a surface of the second IC nearest the first IC. An etch isolation structure is arranged beneath the surface of the second IC and encloses a sacrificial region which is arranged on either side of the second bonding structure and which is arranged in the second IC.
    Type: Application
    Filed: March 5, 2015
    Publication date: May 26, 2016
    Inventors: Yi-Heng Tsai, Yi-Hsien Chang, Chun-Ren Cheng, Chun-Wen Cheng, Tzu-Heng Wu, Wei-Cheng Shen