Patents by Inventor YI HSIN CHANG

YI HSIN CHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10896983
    Abstract: The instant disclosure provides an optical component packaging structure which includes a far-infrared sensor chip, a first metal layer, a packaging housing and a covering member. The far-infrared sensor chip includes a semiconductor substrate and a semiconductor stack structure. The semiconductor substrate has a first surface, a second surface which is opposite to the first surface, and a cavity. The semiconductor stack structure is disposed on the first surface of the semiconductor substrate, and a part of the semiconductor stack structure is located above the cavity. The first metal layer is disposed on the second surface of the semiconductor substrate, the packaging housing is used to encapsulate the far-infrared sensor chip and expose at least a part of the far-infrared sensor chip, and the covering member is disposed above the semiconductor stack structure.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: January 19, 2021
    Assignee: PIXART IMAGING INC.
    Inventors: Yi-Chang Chang, Yen-Hsin Chen, Chi-Chih Shen
  • Patent number: 10879306
    Abstract: A micro semiconductor structure is provided. The micro semiconductor structure includes a substrate, a plurality of micro semiconductor devices disposed on the substrate, and a first supporting layer disposed between the substrate and the micro semiconductor devices. Each of the micro semiconductor devices has a first electrode and a second electrode disposed on a lower surface of the micro semiconductor devices. The lower surface includes a region, wherein the region is between the first electrode and the second electrode. An orthographic projection of the first supporting layer on the substrate at least overlaps an orthographic projection of a portion of the region on the substrate. The first supporting layer directly contacts the region.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: December 29, 2020
    Assignee: PLAYNITRIDE DISPLAY CO., LTD.
    Inventors: Chih-Ling Wu, Ying-Tsang Liu, Pei-Hsin Chen, Yi-Chun Shih, Yi-Ching Chen, Yu-Chu Li, Huan-Pu Chang, Yu-Yun Lo, Yi-Min Su, Tzu-Yang Lin, Yu-Hung Lai
  • Publication number: 20200397609
    Abstract: An artificial stoma device includes a hollow first unit and a second unit that are adapted to be respectively inserted into an upstream section and a downstream section of an intestine via an opening of a skin tissue and via a radial side opening of the intestine. The first unit has inlet and outlet portions. The inlet portion has an inlet opening at a distal end thereof that is adapted for facing the upstream section of the intestine. The outlet portion is connected to the inlet portion, and has an outlet opening that is opposite to and in spatial communication with the inlet opening and that is adapted to be exposed from the skin tissue via the opening. The inlet portion, the outlet portion and the second unit are molded as one piece.
    Type: Application
    Filed: June 24, 2019
    Publication date: December 24, 2020
    Inventor: Yi-Hsin CHANG
  • Patent number: 10852786
    Abstract: A venting grate includes a main portion, a first venting area, and a second venting area. The first venting area is defined by first, second, third, and fourth edges. Each of the first, second, third, and fourth edges extend from the main portion. The second venting area is defined by fifth, sixth, seventh, and eighth edges. Each of the fifth, sixth, seventh, and eighth edges extend from the main portion. The third edge and the fifth edge extend away from the main portion of the venting grate and angle together to form a pointed edge between the first and second venting areas.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: December 1, 2020
    Assignee: Dell Products, L.P.
    Inventors: Chuck Lien, Yi-Hsin Kuan, Chuan Chieh (Dennis) Tseng, Chin-Chia Chang, Richard A. Crisp, Timothy C. Dearborn
  • Publication number: 20200365769
    Abstract: A semiconductor device is provided, which includes a base, a semiconductor structure and a conductive reflective structure. The base has a first surface and a second surface opposite to the first surface. The semiconductor structure is located on the first surface. The conductive reflective structure is located on the second surface and includes a metal oxide structure and a metal structure. The metal oxide structure is located between the metal structure and the base. The metal oxide structure physically contacts the second surface.
    Type: Application
    Filed: May 15, 2020
    Publication date: November 19, 2020
    Inventors: Yao-Ru CHANG, Wen-Luh LIAO, Yung-Fu CHANG, Hsiang CHANG, Meng-Yang CHEN, Yun-Hsin PANG, Yi HSIAO
  • Patent number: 10809990
    Abstract: The disclosure provides an electronic system, a method for instructing an installation of the electronic system, and a computer program product. The electronic system includes a plurality of electronic device sets, a packing box, and a printed matter. The packing box is segmented into a plurality of containing packages, wherein each of the containing packages contains one of the electronic device sets, and the containing packages are labelled with a plurality of sequential numbers corresponding to an installation order of the electronic device sets contained therein. The printed matter is printed with downloading information related to installation software for providing a plurality of installation instructions of sequentially installing the electronic device sets one by one after being installed with the installation software.
    Type: Grant
    Filed: September 3, 2018
    Date of Patent: October 20, 2020
    Assignee: HTC Corporation
    Inventors: Ying-Jing Wang, Yi-Hsin Chang
  • Publication number: 20200273754
    Abstract: Integrated circuit devices having optimized fin critical dimension loading are disclosed herein. An exemplary integrated circuit device includes a core region that includes a first multi-fin structure and an input/output region that includes a second multi-fin structure. The first multi-fin structure has a first width and the second multi-fin structure has a second width. The first width is greater than the second width. In some implementations, the first multi-fin structure has a first fin spacing and the second multi-fin structure has a second fin spacing. The first fin spacing is less than the second fin spacing. In some implementations, a first adjacent fin pitch of the first multi-fin structure is greater than or equal to three times a minimum fin pitch and a second adjacent fin pitch of the second multi-fin structure is less than or equal to two times the minimum fin pitch.
    Type: Application
    Filed: May 11, 2020
    Publication date: August 27, 2020
    Inventors: Chia Ming Liang, Yi-Shien Mor, Huai-Hsien Chiu, Chi-Hsin Chang, Jin-Aun Ng, Yi-Juei Lee
  • Publication number: 20200258784
    Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.
    Type: Application
    Filed: May 1, 2020
    Publication date: August 13, 2020
    Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
  • Publication number: 20200202483
    Abstract: A video processing system includes a main chip and a processing chip. The main chip receives first data. The processing chip is coupled to the main chip, and receives second data and to perform a video processing on at least one of the first data transmitted from the main chip and the second data, in order to drive a display panel. First video carried on the first data or second video on the second data has a first resolution, and the first resolution is at least 8K ultra high definition.
    Type: Application
    Filed: February 28, 2020
    Publication date: June 25, 2020
    Inventors: Yi-Shu Chang, Cheng-Hsin Chang, Hsu-Jung Tung, Chun-Hsing Hsieh, Sen-Huang Tang
  • Patent number: 10692769
    Abstract: Integrated circuit devices having optimized fin critical dimension loading are disclosed herein. An exemplary integrated circuit device includes a core region that includes a first multi-fin structure and an input/output region that includes a second multi-fin structure. The first multi-fin structure has a first width and the second multi-fin structure has a second width. The first width is greater than the second width. In some implementations, the first multi-fin structure has a first fin spacing and the second multi-fin structure has a second fin spacing. The first fin spacing is less than the second fin spacing. In some implementations, a first adjacent fin pitch of the first multi-fin structure is greater than or equal to three times a minimum fin pitch and a second adjacent fin pitch of the second multi-fin structure is less than or equal to two times the minimum fin pitch.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: June 23, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chia Ming Liang, Yi-Shien Mor, Huai-Hsien Chiu, Chi-Hsin Chang, Jin-Aun Ng, Yi-Juei Lee
  • Publication number: 20200185243
    Abstract: A carrier structure suitable for transferring or supporting a plurality of micro devices includes a carrier and a plurality of transfer units. The carrier has a carrier surface and a plurality of recesses disposed on the carrier surface. The transfer units are respectively disposed in the recesses and a plurality of transferring surfaces are exposed. Each micro device has a device surface. The transferring surface of each transfer unit is configured to be connected to the device surface of the corresponding micro device. A micro device structure including the carrier structure is also provided.
    Type: Application
    Filed: September 25, 2019
    Publication date: June 11, 2020
    Applicant: PlayNitride Display Co., Ltd.
    Inventors: Pei-Hsin Chen, Yi-Chun Shih, Yi-Ching Chen, Ying-Tsang Liu, Yu-Chu Li, Huan-Pu Chang, Tzu-Yang Lin, Yu-Hung Lai
  • Publication number: 20200172393
    Abstract: Methods for improving wafer bonding performance are disclosed herein. In some embodiments, a method for bonding a pair of semiconductor substrates is disclosed. The method includes: processing at least one of the pair of semiconductor substrates, and bonding the pair of semiconductor substrates together. Each of the pair of semiconductor substrates is processed by: performing at least one chemical vapor deposition (CVD), and performing at least one chemical mechanical polishing (CMP). One of the at least one CVD is performed after all CMP performed before bonding.
    Type: Application
    Filed: November 26, 2019
    Publication date: June 4, 2020
    Inventors: Chien-Wei CHANG, Ya-Jen SHEUH, Ren-Dou LEE, Yi-Chih CHANG, Yi-Hsun CHIU, Yuan-Hsin CHI
  • Publication number: 20200176509
    Abstract: A micro semiconductor structure is provided. The micro semiconductor structure includes a substrate, at least one supporting layer, and at least one micro semiconductor device. The supporting layer includes at least one upper portion and a bottom portion, wherein the upper portion extends in a first direction. The length L1 of the upper portion in the first direction is greater than the length L2 of the bottom portion in the first direction. Furthermore, the bottom surface of the micro semiconductor device is in direct contact with the upper portion of the supporting layer.
    Type: Application
    Filed: June 10, 2019
    Publication date: June 4, 2020
    Applicant: PlayNitride Display Co., Ltd.
    Inventors: Ying-Tsang Liu, Pei-Hsin Chen, Yi-Chun Shih, Yi-Ching Chen, Yu-Chu Li, Huan-Pu Chang, Tzu-Yang Lin, Yu-Hung Lai
  • Publication number: 20200176508
    Abstract: A micro semiconductor structure is provided. The micro semiconductor structure includes a substrate, a plurality of micro semiconductor devices disposed on the substrate, and a first supporting layer disposed between the substrate and the micro semiconductor devices. Each of the micro semiconductor devices has a first electrode and a second electrode disposed on a lower surface of the micro semiconductor devices. The lower surface includes a region, wherein the region is between the first electrode and the second electrode. An orthographic projection of the first supporting layer on the substrate at least overlaps an orthographic projection of a portion of the region on the substrate. The first supporting layer directly contacts the region.
    Type: Application
    Filed: June 7, 2019
    Publication date: June 4, 2020
    Applicant: PlayNitride Display Co., Ltd.
    Inventors: Chih-Ling WU, Ying-Tsang LIU, Pei-Hsin CHEN, Yi-Chun SHIH, Yi-Ching CHEN, Yu-Chu LI, Huan-Pu CHANG, Yu-Yun LO, Yi-Min SU, Tzu-Yang LIN, Yu-Hung LAI
  • Patent number: 10672864
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: June 2, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tzu-Chin Wu, Wei-Hsin Liu, Yi-Wei Chen, Chia-Lung Chang, Jui-Min Lee, Po-Chun Chen, Li-Wei Feng, Ying-Chiao Wang, Wen-Chieh Lu, Chien-Ting Ho, Tsung-Ying Tsai, Kai-Ping Chen
  • Publication number: 20200147514
    Abstract: An atmospheric water generator for extracting water droplets from ambient air includes an insulating substrate, a plurality of electrode film units, and a liquid crystal/polymer composite film. Each of surface regions of the liquid crystal/polymer composite film has a plurality of liquid crystal molecules each having a hydrophilic functional group and a hydrophobic moiety. Each of the surface regions normally has one of hydrophilic and hydrophobic properties. When a voltage is applied to one of the electrode film units, the respective surface region is switched to have the other one of hydrophilic and hydrophobic properties, to thereby allow the water droplets condensed from the ambient air to move on the surface regions.
    Type: Application
    Filed: January 17, 2019
    Publication date: May 14, 2020
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Yi-Hsin LIN, Chia-Ming CHANG
  • Patent number: 10651090
    Abstract: Integrated circuit devices having optimized fin critical dimension loading are disclosed herein. An exemplary integrated circuit device includes a core region that includes a first multi-fin structure and an input/output region that includes a second multi-fin structure. The first multi-fin structure has a first width and the second multi-fin structure has a second width. The first width is greater than the second width. In some implementations, the first multi-fin structure has a first fin spacing and the second multi-fin structure has a second fin spacing. The first fin spacing is less than the second fin spacing. In some implementations, a first adjacent fin pitch of the first multi-fin structure is greater than or equal to three times a minimum fin pitch and a second adjacent fin pitch of the second multi-fin structure is less than or equal to two times the minimum fin pitch.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chia Ming Liang, Yi-Shien Mor, Huai-Hsien Chiu, Chi-Hsin Chang, Jin-Aun Ng, Yi-Juei Lee
  • Patent number: D891504
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: July 28, 2020
    Assignee: TDK TAIWAN CORP.
    Inventors: Fu-Yuan Wu, Kun-Shih Lin, Shang-Yu Hsu, Yi-Ho Chen, Shih-Ting Huang, Shou-Jen Liu, Chien-Lun Huang, Yi-Hsin Nieh, Chen-Chi Kuo, Chia-Pin Hsu, Yu-Huai Liao, Shin-Hua Chen, Yu-Cheng Lin, Shao-Chung Chang, Kuo-Chun Kao, Chia-Hsiu Liu, Chao-Chun Chang, Yuan-Shih Liao
  • Patent number: D902981
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 24, 2020
    Assignee: TDK TAIWAN CORP.
    Inventors: Fu-Yuan Wu, Kun-Shih Lin, Shang-Yu Hsu, Yi-Ho Chen, Shih-Ting Huang, Shou-Jen Liu, Chien-Lun Huang, Yi-Hsin Nieh, Chen-Chi Kuo, Chia-Pin Hsu, Yu-Huai Liao, Shin-Hua Chen, Yu-Cheng Lin, Shao-Chung Chang, Kuo-Chun Kao, Chia-Hsiu Liu, Chao-Chun Chang, Yuan-Shih Liao
  • Patent number: D902982
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 24, 2020
    Assignee: TDK TAIWAN CORP.
    Inventors: Fu-Yuan Wu, Kun-Shih Lin, Shang-Yu Hsu, Yi-Ho Chen, Shih-Ting Huang, Shou-Jen Liu, Chien-Lun Huang, Yi-Hsin Nieh, Chen-Chi Kuo, Chia-Pin Hsu, Yu-Huai Liao, Shin-Hua Chen, Yu-Cheng Lin, Shao-Chung Chang, Kuo-Chun Kao, Chia-Hsiu Liu, Chao-Chun Chang, Yuan-Shih Liao