Patents by Inventor Yi-Hsun Chen

Yi-Hsun Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10940438
    Abstract: The present invention provides an omniphobic membrane and application thereof. The omniphobic membrane comprises a porous substrate which has a pore size between 0.4 and 2 ?m, a top coat, and an interface layer between the porous substrate and the top coat, and the omniphobic membrane has a carbon/silicon ratio between 40 and 60, and a hierarchical re-entrant structure. Furthermore, both of a process for fabricating the omniphobic membrane and a method for desalination of a liquid by membrane distillation are provided in the present invention.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: March 9, 2021
    Assignee: NATIONAL TAIWAN UNIVERSITY
    Inventors: Kuo-Lun Tung, Allen Huang, Liang-Hsun Chen, Yi-Rui Chen, Chien-Hua Chen, Che-Chen Hsu, Feng-Yu Tsai
  • Patent number: 10923029
    Abstract: A pixel circuit including a light-emitting element, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a storage capacitor is provided. The third transistor is coupled to the second transistor. The fourth transistor is coupled to the second transistor. The storage capacitor is coupled between the first transistor and the fourth transistor. The fifth transistor is coupled to the fourth transistor. The sixth transistor is coupled to the fourth transistor. The seventh transistor is coupled to the fourth transistor and the light-emitting element. The eighth transistor is coupled to the first transistor.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: February 16, 2021
    Assignee: Au Optronics Corporation
    Inventors: Yi-Chiung Chen, Mao-Hsun Cheng
  • Publication number: 20210035969
    Abstract: A high-voltage circuitry device is provided. The high-voltage circuitry device includes a high-voltage transistor, a protection component and a feedback component. The high-voltage transistor has a gate, a drain and a source. The protection component is coupled between the source of the high-voltage transistor and the ground. When a current corresponding to an electrostatic discharge (ESD) event flows through the drain of the high-voltage transistor, the current flows from the drain of the high-voltage transistor to the ground through the high-voltage transistor and the protection component. The feedback component is coupled between the protection component, the ground and the gate of the high-voltage transistor. When the ESD event occurs, the feedback component enables the high-voltage transistor to stay on a turned-on state to pass the current.
    Type: Application
    Filed: November 18, 2019
    Publication date: February 4, 2021
    Inventors: Yi-Hao CHEN, Tsu-Yi WU, Chih-Hsun LU, Po-An CHEN, Chun-Chieh LIU
  • Publication number: 20210015757
    Abstract: The present disclosure relates to mesoporous silica nanoparticles having modifications on the surface of the (extended) mesopores, which can be further loaded with one or more types of bioactive ingredients within the (extended) mesopores mesopores, processes of preparing the same and applications of the same.
    Type: Application
    Filed: July 17, 2020
    Publication date: January 21, 2021
    Inventors: Hardy Wai Hong CHAN, Chung-Yuan MOU, Cheng-Hsun WU, Si-Han WU, Yi-Ping CHEN, Rong-Lin ZHANG
  • Publication number: 20210015943
    Abstract: The present disclosure relates to a field of hollow silica nanospheres. Particularly, the present disclosure relates to silica nanoparticles as adjuvant to induce or enhance immune response or as carrier to deliver antigen to a body.
    Type: Application
    Filed: July 17, 2020
    Publication date: January 21, 2021
    Inventors: Chung-Yuan MOU, Cheng-Hsun WU, Si-Han WU, Yi-Ping CHEN
  • Publication number: 20210013205
    Abstract: A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin, third fin, and fourth fin. A dielectric layer is formed over fins and a work function adjustment layer is formed over dielectric layer. A hard mask is formed covering third and fourth fins. A first conductive material layer is formed over first fin and not over second fin. A second conductive material layer is formed over first and second fins. A first metal gate electrode fill material is formed over first and second fins. The hard mask covering third and fourth fins is removed. A third conductive material layer is formed over third fin and not over fourth fin. A fourth conductive material layer is formed over third and fourth fins, and a second metal gate electrode fill material is formed over third and fourth fins.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Inventors: Chia-Chun LIAO, Chun-Sheng LIANG, Shu-Hui WANG, Shih-Hsun CHANG, Yi-Jen CHEN
  • Patent number: 10891847
    Abstract: Examples herein disclose an apparatus. The apparatus includes a network interface controller (NIC) port to be dedicated to a management functionality of a server. The apparatus also includes a light emitting diode (LED), coupled to the NIC port, to provide a visible indication that the NIC port is dedicated to the management functionality of the server.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: January 12, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Min-Lung Ke, Peter Liao, Chun-Hua Huang, Chih-Chieh Wang, Yi-Hsun Chen
  • Patent number: 10879229
    Abstract: A method of forming an integrated circuit structure includes placing a tap cell layout pattern on a layout level, placing a set of standard cell layout patterns adjacent to the tap cell layout pattern, and manufacturing the integrated circuit structure based on at least one of the layout patterns. The placing the first well layout pattern includes placing a first layout pattern extending in a first direction and having a first width, placing a second layout pattern adjacent to the first layout pattern, and having a second width greater than the first width, and placing a first implant layout pattern on a second layout level, extending in the first direction, overlapping the first layout pattern and having a third width greater than the first width.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kam-Tou Sio, Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Yi-Hsun Chiu
  • Patent number: 10878744
    Abstract: A pixel driving circuit utilizing a transistor having two gate ends as the driving unit for pixels of a display panel to provide a stable driving current to compensate for the variation of threshold voltages of transistors in different pixels and to improve the uniformity of the brightness of the display panel.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: December 29, 2020
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Mao-Hsun Cheng, Cheng-Han Huang, Mei-Sheng Ma, Yi-Chiung Chen, Hsiang-Sheng Chang, Po-Jung Wu, Yung-Chih Chen, Ching-Sheng Cheng
  • Publication number: 20200395253
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate, wherein the gate stack has a first portion and a second portion under the first portion, and the first portion is wider than the second portion. The semiconductor device structure includes a first spacer and a second spacer over opposite sides of the gate stack. The first spacer has a first upper portion and a first lower portion, the second spacer has a second upper portion and a second lower portion. The first spacer has a first recess, the first upper portion is between the first recess and the gate stack, the first lower portion is under the first recess, and the first recess has a first inner wall facing away from the gate stack.
    Type: Application
    Filed: August 28, 2020
    Publication date: December 17, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Heng TSAI, Chun-Sheng LIANG, Pei-Lin WU, Yi-Ren CHEN, Shih-Hsun CHANG
  • Publication number: 20200395938
    Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.
    Type: Application
    Filed: May 26, 2020
    Publication date: December 17, 2020
    Inventors: Chi-Lin Liu, Shang-Chih Hsieh, Jian-Sing Li, Wei-Hsiang Ma, Yi-Hsun Chen, Cheok-Kei Lei
  • Publication number: 20200357793
    Abstract: A method of forming an integrated circuit structure includes placing a tap cell layout pattern on a layout level, placing a set of standard cell layout patterns adjacent to the tap cell layout pattern, and manufacturing the integrated circuit structure based on at least one of the layout patterns. The placing the first well layout pattern includes placing a first layout pattern extending in a first direction and having a first width, placing a second layout pattern adjacent to the first layout pattern, and having a second width greater than the first width, and placing a first implant layout pattern on a second layout level, extending in the first direction, overlapping the first layout pattern and having a third width greater than the first width.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Kam-Tou SIO, Chih-Liang CHEN, Charles Chew-Yuen YOUNG, Hui-Zhong ZHUANG, Jiann-Tyng TZENG, Yi-Hsun CHIU
  • Publication number: 20200345649
    Abstract: The present disclosure relates to mesoporous silica nanoparticles (MSNs) with specific modifications as drug delivery systems containing both tumor targeting and blood-brain barrier (BBB) penetration properties suitable for cancer treatment and/or CNS disease treatment. The present disclosure also relates to method of preparing MSNs and the MSNs prepared by the method as described herein.
    Type: Application
    Filed: April 30, 2020
    Publication date: November 5, 2020
    Inventors: Cheng-Hsun WU, Yi-Ping CHEN, Si-Han WU, Chung-Yuan MOU
  • Publication number: 20200338142
    Abstract: An isolated lactic acid bacteria strain: Bifidobacterium longum subsp. longum OLP-01 strain for increasing exercise performance and ameliorating fatigue is disclosed. A variety of animal experiments have proved that OLP-01 not only effectively improves muscle strength and swimming endurance but also significantly reduces fatigue-related biochemical indicators, including blood lactate, blood urea nitrogen and the activity of creatine kinase.
    Type: Application
    Filed: July 17, 2019
    Publication date: October 29, 2020
    Inventors: Chi-Chang HUANG, Wei-Ling CHEN, Mon-Chien LEE, Yi-Ju HSU, Hsieh-Hsun HO, Pei-Shan HSIEH
  • Patent number: 10790283
    Abstract: A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin, third fin, and fourth fin. A dielectric layer is formed over fins and a work function adjustment layer is formed over dielectric layer. A hard mask is formed covering third and fourth fins. A first conductive material layer is formed over first fin and not over second fin. A second conductive material layer is formed over first and second fins. A first metal gate electrode fill material is formed over first and second fins. The hard mask covering third and fourth fins is removed. A third conductive material layer is formed over third fin and not over fourth fin. A fourth conductive material layer is formed over third and fourth fins, and a second metal gate electrode fill material is formed over third and fourth fins.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: September 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Chun Liao, Chun-Sheng Liang, Shu-Hui Wang, Shih-Hsun Chang, Yi-Jen Chen
  • Publication number: 20200303435
    Abstract: A semiconductor structure includes an ILD disposed over a semiconductive substrate, an isolation disposed between the semiconductive substrate and the ILD, and a conductive pad disposed within the semiconductive substrate, the isolation and the ILD. A top surface of the conductive pad is substantially parallel with two surfaces of the semiconductive substrate. The top surface of the conductive pad is between the two surfaces of the semiconductive substrate. Sidewalls of the conductive pad are in direct contact with the ILD and the isolation.
    Type: Application
    Filed: June 9, 2020
    Publication date: September 24, 2020
    Inventors: CHIA-YU WEI, CHIN-HSUN HSIAO, YI-HSING CHU, YEN-LIANG LIN, YUNG-LUNG HSU, HSIN-CHI CHEN
  • Patent number: 10763178
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack has a first upper portion and a first lower portion, and the first upper portion is wider than the first lower portion. The semiconductor device structure includes a spacer layer surrounding the gate stack. The spacer layer has a second upper portion and a second lower portion. The second upper portion is thinner than the second lower portion.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Heng Tsai, Chun-Sheng Liang, Pei-Lin Wu, Yi-Ren Chen, Shih-Hsun Chang
  • Patent number: 10734377
    Abstract: An integrated circuit structure includes a first well, and a first and a second set of implants. The first well includes a first dopant type, a first portion extending in a first direction and having a first width, and a second portion adjacent to the first portion. The second portion extends in the first direction and has a second width greater than the first width. The first set of implants are in the first portion of the first well, and the second set of implants are in the second portion of the first well. At least one implant of the first set of implants being configured to be coupled to a first supply voltage. Each implant of the second set of implants having a second dopant type different from a first dopant type of the first set of implants.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kam-Tou Sio, Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Yi-Hsun Chiu
  • Patent number: D912042
    Type: Grant
    Filed: September 3, 2018
    Date of Patent: March 2, 2021
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Hsin Yeh, Jyh-Chyang Tzou, Han-Tsai Liu, Pai-Feng Chen, Yi-Hsun Liu
  • Patent number: D914010
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: March 23, 2021
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Hsin Yeh, Jyh-Chyang Tzou, Han-Tsai Liu, Pai-Feng Chen, Yi-Hsun Liu