Patents by Inventor Yi-Hsun Chen

Yi-Hsun Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240139337
    Abstract: The present disclosure relates to a method for treating a cancer and/or cancer metastasis in a subject comprising administering to the subject irinotecan loaded in a mesoporous silica nanoparticle. The present disclosure also provides a conjugate comprising an agent loaded in a mesoporous silica nanoparticle (MSN) defining at least one pore and having at least one functional group on a sidewall of the at least one pore.
    Type: Application
    Filed: November 2, 2022
    Publication date: May 2, 2024
    Inventors: Cheng-Hsun WU, SI-HAN WU, YI-PING CHEN, RONG-LIN ZHANG, CHUNG-YUAN MOU, Yu-Tse LEE
  • Patent number: 11969450
    Abstract: Disclosed herein are methods for improving gastrointestinal barrier function, alleviating a gastrointestinal barrier dysfunction-associated disorder, and inhibiting growth of enteric pathogenic bacteria using a composition containing Lactobacillus rhamnosus MP108, Bifidobacterium longum subsp. infantis BLI-02, and Bifidobacterium animalis subsp. lactis BB-115, which are deposited at the China General Microbiological Culture Collection Center (CGMCC) respectively under accession numbers CGMCC 21225, CGMCC 15212, and CGMCC 21840. A number ratio of Lactobacillus rhamnosus MP108, Bifidobacterium longum subsp. infantis BLI-02, and Bifidobacterium animalis subsp. lactis BB-115 ranges from 1:0.2:0.67 to 1:9:9.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: April 30, 2024
    Assignee: GLAC BIOTECH CO., LTD.
    Inventors: Hsieh-Hsun Ho, Jui-Fen Chen, Yi-Wei Kuo, Chi-Huei Lin
  • Patent number: 11969447
    Abstract: A composition for promoting defecation includes a cell culture of at least one lactic acid bacterial strain which is substantially free of cells. The least one lactic acid bacterial strain is selected from the group consisting of Lactobacillus salivarius subsp. salicinius AP-32, Bifidobacterium animalis subsp. lactis CP-9, and Lactobacillus acidophilus TYCA06, which are respectively deposited at the Bioresource Collection and Research Center (BCRC) under accession numbers BCRC 910437, BCRC 910645 and BCRC 910813. Also disclosed is a method for promoting defecation, including administering to a subject in need thereof an effective amount of the composition.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: April 30, 2024
    Assignee: GLAC BIOTECH CO., LTD.
    Inventors: Hsieh-Hsun Ho, Ching-Wei Chen, Yi-Wei Kuo, Yu-Fen Huang, Cheng-Chi Lin
  • Publication number: 20240136383
    Abstract: A semiconductor device includes a single-layered dielectric layer, a conductive line, a conductive via and a conductive pad. The conductive line and the conductive via are disposed in the single-layered dielectric layer. The conductive pad is extended into the single-layered dielectric layer to electrically connected to the conductive line.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chien Ku, Huai-Jen Tung, Keng-Ying Liao, Yi-Hung Chen, Shih-Hsun Hsu, Yi-Fang Yang
  • Patent number: 11963987
    Abstract: At least one isolated lactic acid bacteria strains selected from the following: TSP05 (Lactobacillus plantarum), TSF331 (Lactobacillus fermentum) and TSR332 (Lactobacillus reuteri) is provided. The above-mentioned active or inactive lactic acid bacteria strains have a function of hepatoprotection and is used in a form of a food composition or a pharmaceutical composition.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: April 23, 2024
    Assignee: GLAC BIOTECH CO., LTD.
    Inventors: Hsieh-Hsun Ho, Yi Wei Kuo, Jui-Fen Chen, Ching-Wei Chen
  • Patent number: 11963295
    Abstract: Provided are a circuit apparatus, a manufacturing method thereof, and a circuit system. The circuit apparatus includes a flexible circuit board, a flexible packaging material layer and an electronic device. The flexible circuit board has at least one hollow pattern, wherein the flexible circuit board has an inner region and a peripheral region surrounding the inner region, and has a first surface and a second surface opposite to each other. The flexible packaging material layer is disposed in the at least one hollow pattern. The electronic device is disposed on the first surface of the flexible circuit board and electrically connected with the flexible circuit board.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: April 16, 2024
    Assignee: Industrial Technology Research Institute
    Inventors: Hung-Hsien Ko, Yi-Cheng Lu, Heng-Yin Chen, Hao-Wei Yu, Te-Hsun Lin
  • Patent number: 11942420
    Abstract: A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Guo-Huei Wu, Hui-Zhong Zhuang, Chih-Liang Chen, Cheng-Chi Chuang, Shang-Wen Chang, Yi-Hsun Chiu
  • Publication number: 20240096701
    Abstract: A device includes: a stack of semiconductor nanostructures; a gate structure wrapping around the semiconductor nanostructures, the gate structure extending in a first direction; a source/drain region abutting the gate structure and the stack in a second direction transverse the first direction; a contact structure on the source/drain region; a backside conductive trace under the stack, the backside conductive trace extending in the second direction; a first through via that extends vertically from the contact structure to a top surface of the backside dielectric layer; and a gate isolation structure that abuts the first through via in the second direction.
    Type: Application
    Filed: May 17, 2023
    Publication date: March 21, 2024
    Inventors: Chun-Yuan CHEN, Huan-Chieh SU, Ching-Wei TSAI, Shang-Wen CHANG, Yi-Hsun CHIU, Chih-Hao WANG
  • Publication number: 20240092662
    Abstract: A method for removing a heavy metal from water includes subjecting a microbial solution containing a liquid culture of a urease-producing bacterial strain and a reaction solution containing a manganese compound and urea to a microbial-induced precipitation reaction, so as to obtain biomineralized manganese carbonate (MnCO3) particles, admixing the biomineralized MnCO3 particles with water containing a heavy metal, so that the biomineralized MnCO3 particles adsorb the heavy metal in the water to form a precipitate, and removing the precipitate from the water.
    Type: Application
    Filed: February 9, 2023
    Publication date: March 21, 2024
    Inventors: Chien-Yen CHEN, Yi-Hsun HUANG, Pin-Yun LIN, Anggraeni Kumala DEWI, Koyeli DAS, Uttara SUKUL, Tsung-Hsien CHEN, Raju Kumar SHARMA, Cheng-Kang LU, Chung-Ming LU
  • Publication number: 20240088148
    Abstract: A semiconductor device includes a substrate, a stack of semiconductor nanosheets, a dielectric wall, and a gate structure. The substrate includes a nanosheet mesa, and the stack of semiconductor nanosheets is disposed on the nanosheet mesa. The dielectric wall crosses through the nanosheet mesa and the stack of semiconductor nanosheets. The gate structure wraps the stack of semiconductor nanosheets and crosses over the dielectric wall, wherein a top of the dielectric wall has a recess.
    Type: Application
    Filed: January 11, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Ren Chen, Chung-Ting Li, Shih-Hsun Chang
  • Publication number: 20240068705
    Abstract: This disclosure is a condensate evaporation device. An air conditioning apparatus includes a compressor, an evaporator and a condenser connected with one another. A water tray is arranged to receive the condensate. A water distribution module includes a water separator base and a water separator piece. The water separator piece and the water separator base are combined to define a water channel. The condensate flows through the water channel to evenly flow out. A multi-folded water absorbing body is arranged on one side of the water separator base to absorb the condensate flowed out from the water separator base. The water tank is arranged on a bottom side of the multi-folded water absorbing body. A fan is arranged on one side of the multi-folded water absorbing body. Accordingly, the condensate may be evaporated efficiently.
    Type: Application
    Filed: January 18, 2023
    Publication date: February 29, 2024
    Inventors: Chao-Hsien CHAN, Yi-Chung CHOU, Chun-Hsun CHEN
  • Patent number: 11913047
    Abstract: A method for producing ?-aminobutyric acid includes cultivating, in a culture medium containing glutamic acid or a salt thereof, a probiotic composition including at least one lactic acid bacterial strain selected from the group consisting of Bifidobacterium breve CCFM1025 which is deposited at the Guangdong Microbial Culture Collection Center under an accession number GDMCC 60386, Lactobacillus acidophilus TYCA06, Lactobacillus plantarum LPL28, and Bifidobacterium longum subsp. infantis BLI-02 which are deposited at the China General Microbiological Culture Collection Center respectively under accession numbers CGMCC 15210, CGMCC 17954, and CGMCC 15212, Lactobacillus salivarius subsp. salicinius AP-32 which is deposited at the China Center for Type Culture Collection under an accession number CCTCC M 2011127, and combinations thereof.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: February 27, 2024
    Assignee: GLAC BIOTECH CO., LTD.
    Inventors: Hsieh-Hsun Ho, Ching-Wei Chen, Yu-Fen Huang, Chen-Hung Hsu, Wen-Yang Lin, Yi-Wei Kuo, Shin-Yu Tsai
  • Publication number: 20240037309
    Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.
    Type: Application
    Filed: June 30, 2023
    Publication date: February 1, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Lin Liu, Shang-Chih Hsieh, Jian-Sing Li, Wei-Hsiang Ma, Yi-Hsun Chen, Cheok-Kei Lei
  • Patent number: 11694012
    Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: July 4, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Chi-Lin Liu, Shang-Chih Hsieh, Jian-Sing Li, Wei-Hsiang Ma, Yi-Hsun Chen, Cheok-Kei Lei
  • Patent number: 11608319
    Abstract: A compound represented by Formula (I), a pharmaceutically acceptable salt or ester, hydrate, solvate or crystalline form thereof is provided: The compound represented by Formula (I) is a ?-amino acid derivative, and in Formula (I) X is a single bond or O; Y is NH or C?O; Z is C?O, C?S, NH, W is C or N; A is a single bond, O, OH, OCH2, a heterocycle or N3; R1 is H or F; R2 is H, F, OH, CF3, CH2OH, CHO or R3 is H; n is 0 or 1; and m is 0 or 1.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: March 21, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chih-Wei Fu, Chih-Peng Liu, Yi-Hsun Chen, Chia-Mu Tu, Chiu-Lien Hung
  • Publication number: 20220363645
    Abstract: A compound represented by Formula (I), a pharmaceutically acceptable salt or ester, hydrate, solvate or crystalline form thereof is provided: The compound represented by Formula (I) is a ?-amino acid derivative, and in Formula (I) X is a single bond or O; Y is NH or C?O; Z is C?O, C?S, NH, W is C or N; A is a single bond, O, OH, OCH2, a heterocycle or N3; R1 is H or F; R2 is H, F, OH, CF3, CH2OH, CHO or R3 is H; n is 0 or 1; and m is 0 or 1.
    Type: Application
    Filed: December 10, 2020
    Publication date: November 17, 2022
    Applicant: Industrial Technology Research Institute
    Inventors: Chih-Wei FU, Chih-Peng LIU, Yi-Hsun CHEN, Chia-Mu TU, Chiu-Lien HUNG
  • Publication number: 20220327275
    Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 13, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Lin Liu, Shang-Chih Hsieh, Jian-Sing Li, Wei-Hsiang Ma, Yi-Hsun Chen, Cheok-Kei Lei
  • Patent number: 11392743
    Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Lin Liu, Shang-Chih Hsieh, Jian-Sing Li, Wei-Hsiang Ma, Yi-Hsun Chen, Cheok-Kei Lei
  • Publication number: 20220020986
    Abstract: An electrode material of a lithium-ion battery is provided. The electrode material of the lithium-ion battery has 5 to 70 parts by weight of unbuffered active material; and 30 to 95 parts by weight of buffered active material. By adding a specific proportion of a buffered material (such as the graphite material particles), the electrode material of the lithium-ion battery avoids or reduces breakage or cracking of the unbuffered active material themselves or the shell thereof during a rolling step, so a cycle life of a battery can be improved.
    Type: Application
    Filed: July 13, 2021
    Publication date: January 20, 2022
    Inventors: Po-chin CHEN, Wei-chih CHEN, Yi-hsun CHEN, Hsiang-yu HSU, Kai-Chih HSU, Yuan-ping YANG
  • Patent number: 11171851
    Abstract: A server system having functionality of group alerting is disclosed. Said server system comprises: a plurality of server computers having alert notification capabilities, the plurality of server computers being divided into at least one group; and a management console node managing and monitoring the plurality of server computers; wherein the alert notification is issued by a group of the at least one group of the plurality of server computers when a health problem of a server computer in said group of the at least one group of the plurality of server computers occurs.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: November 9, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Liang-Chin Kao, Shang-Ching Hung, Shih-Chiang Chung, An Sheng Huang, Yi-Hsun Chen