Abstract: The invention introduces a method for handling sudden power off recovery, performed by a processing unit of an electronic apparatus, to include: driving a flash interface to program data sent by a host into pseudo single-level cell (pSLC) blocks of multiple logical unit numbers (LUNs) in a single-level cell (SLC) mode with multiple channels after detecting that the electronic apparatus has suffered a sudden power off (SPO), and driving the flash interface to erase memory cells of all the pSLC blocks when data of all pSLC blocks has been read by the host. The pSLC blocks are reserved from being written to in regular operations until the SPO is detected.

Abstract: A storage device includes a flash memory array and a controller. The flash memory array stores a plurality of user data. After the controller finishes initialization, the controller accesses the user data stored in the flash memory array according to a plurality of host commands and an H2F mapping table, and records a plurality of address information about the user data in a powered-ON access table.

Abstract: The invention introduces a method for handling sudden power off recovery, performed by a processing unit of an electronic apparatus, to include: driving a flash interface to program data sent by a host into pseudo single-level cell (pSLC) blocks of multiple logical unit numbers (LUNs) in a single-level cell (SLC) mode with multiple channels after detecting that the electronic apparatus has suffered a sudden power off (SPO), and driving the flash interface to erase memory cells of all the pSLC blocks when data of all pSLC blocks has been read by the host. The pSLC blocks are reserved from being written to in regular operations until the SPO is detected.

Abstract: The invention introduces a method for handling sudden power off recovery, performed by a processing unit of an electronic apparatus, to include: driving a flash interface to program data sent by a host into pseudo single-level cell (pSLC) blocks of multiple logical unit numbers (LUNs) in a single-level cell (SLC) mode with multiple channels after detecting that the electronic apparatus has suffered a sudden power off (SPO). The pSLC blocks are reserved from being written any data in regular operations until the SPO is detected.

Abstract: A data storage device equipped with a plurality of thermometers configured to detect temperature of different regions of a non-volatile memory. A controller of the data storage device is configured to operate the non-volatile memory to heat up a target region of the non-volatile memory according to a regional temperature detected by a target thermometer corresponding to the target region.

Abstract: A method for performing refresh management in a memory device, the memory device and controller thereof are provided. The method may include: monitoring a temperature of the memory device, wherein the temperature is detected through a temperature sensor; updating a recorded highest temperature and a recorded lowest temperature according to said temperature; checking whether a difference between the recorded highest temperature and the recorded lowest temperature is greater than a predetermined temperature threshold; and when the difference is greater than the predetermined temperature threshold, triggering refresh of the memory device.

Abstract: The data storage device includes a first memory having error correction capability, and a controller coupled to the first memory. The controller is configured to calculate an error count of the first memory. The controller is configured to report a message to a host when the controller determines that an alarm condition is satisfied. The alarm condition is related to the error count of the first memory and a threshold count.

Abstract: A data storage device equipped with a plurality of thermometers configured to detect temperature of different regions of a non-volatile memory. A controller of the data storage device is configured to operate the non-volatile memory to heat up a target region of the non-volatile memory according to a regional temperature detected by a target thermometer corresponding to the target region.

Abstract: The invention introduces a method for handling sudden power off recovery, performed by a processing unit of an electronic apparatus, to include: driving a flash interface to program data sent by a host into pseudo single-level cell (pSLC) blocks of multiple logical unit numbers (LUNs) in a single-level cell (SLC) mode with multiple channels after detecting that the electronic apparatus has suffered a sudden power off (SPO). The pSLC blocks are reserved from being written any data in regular operations until the SPO is detected.

Abstract: A preheating procedure for a non-volatile memory that can be used in a wide range of ambient temperatures is shown. The controller of the non-volatile memory operates the non-volatile memory to preheat the non-volatile to a temperature target. The controller avoids writing valid data to the non-volatile memory until preheating the non-volatile memory to the temperature target. The controller may write or read dummy data to or from the non-volatile memory until preheating the non-volatile memory to the temperature target.

Abstract: A storage device includes a flash memory array and a controller. The flash memory array stores a plurality of user data. After the controller finishes initialization, the controller accesses the user data stored in the flash memory array according to a plurality of host commands and an H2F mapping table, and records a plurality of address information about the user data in a powered-ON access table.

Abstract: A storage device includes a flash memory array and a controller. The flash memory array stores a plurality of user data. After the controller finishes initialization, the controller accesses the user data stored in the flash memory array according to a plurality of host commands and an H2F mapping table, and records a plurality of address information about the user data in a powered-ON access table.

Abstract: A preheating procedure for a non-volatile memory that can be used in a wide range of ambient temperatures is shown. The controller of the non-volatile memory operates the non-volatile memory to preheat the non-volatile to a temperature target. The controller avoids writing valid data to the non-volatile memory until preheating the non-volatile memory to the temperature target. The controller may write or read dummy data to or from the non-volatile memory until preheating the non-volatile memory to the temperature target.

Abstract: A hybrid data storage device is shown. In addition to a non-volatile memory, the hybrid data storage device has a volatile memory. A microcontroller of the data storage device generates and maintains a first mapping table and a second mapping table. According to the first mapping table, specific logical addresses are mapped to the volatile memory. The second mapping table records mapping information between logical addresses, including the specific logical addresses, and the non-volatile memory. When the data storage device is powered on, the microcontroller uploads data read from the non-volatile memory to the volatile memory according to the first mapping table and the second mapping table.

Abstract: The data storage device includes a first memory having error correction capability, and a controller coupled to the first memory. The controller is configured to calculate an error count of the first memory. The controller is configured to report a message to a host when the controller determines that an alarm condition is satisfied. The alarm condition is related to the error count of the first memory and a threshold count.

Abstract: A method for performing refresh management in a memory device, the memory device and controller thereof are provided. The method may include: monitoring a temperature of the memory device, wherein the temperature is detected through a temperature sensor; updating a recorded highest temperature and a recorded lowest temperature according to said temperature; checking whether a difference between the recorded highest temperature and the recorded lowest temperature is greater than a predetermined temperature threshold; and when the difference is greater than the predetermined temperature threshold, triggering refresh of the memory device.

Abstract: A storage device includes a flash memory array and a controller. The flash memory array includes a plurality of blocks which are configured to store data. The controller scans the flash memory array during an idle time to confirm the accuracy of the data stored in the flash memory array.

Abstract: A storage device includes a flash memory array and a controller. The flash memory array stores a plurality of user data. After the controller finishes initialization, the controller accesses the user data stored in the flash memory array according to a plurality of host commands and an H2F mapping table, and records a plurality of address information about the user data in a powered-ON access table.

Abstract: A data storage device includes a flash memory, a voltage detection device, and a controller. The flash memory is arranged to store data. The voltage detection device is arranged to detect a supply voltage received by the data storage device. The controller is configured to receive write commands from a host, and perform a prohibition mode when the supply voltage is outside a predetermined range, wherein the write command is arranged to enable the controller to write the flash memory, and the controller is further configured to disable all of the write commands received from the host in the prohibition mode.

Abstract: A data storage device includes a flash memory, a voltage detection device, and a controller. The flash memory is arranged to store data. The voltage detection device is arranged to detect a supply voltage received by the data storage device. The controller is configured to receive write commands from a host, and perform a prohibition mode when the supply voltage is outside a predetermined range, wherein the write command is arranged to enable the controller to write the flash memory, and the controller is further configured to disable all of the write commands received from the host in the prohibition mode.