Patents by Inventor Yi-Hui LEE

Yi-Hui LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9941215
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a first gate structure is formed on the substrate, a first spacer is formed around the first gate structure, and an interlayer dielectric (ILD) layer is formed around the first spacer. Next, a first etching process is performed to remove part of the ILD layer for forming a recess, a second etching process is performed to remove part of the first spacer for expanding the recess, and a contact plug is formed in the recess.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: April 10, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Chih-Sen Huang
  • Patent number: 9922882
    Abstract: A manufacturing method of a semiconductor structure includes the following steps. A substrate is provided, and an epitaxial structure is formed on the substrate. A first dielectric layer covering the epitaxial structure and the substrate is formed. A patterned hard mask layer is formed on the first dielectric layer. A second dielectric layer is formed on the patterned hard mask layer and the first dielectric layer. A patterned photoresist layer is formed on the second dielectric layer. A dry etching process is performed with the pattern hard mask layer and the patterned photoresist layer as masks. The dry etching process forms a contact opening in the first dielectric layer, and the contact opening exposes at least a part of the epitaxial structure. A wet etching process is performed after the dry etching process, and the wet etching process removes the patterned hard mask layer and the second dielectric layer together.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: March 20, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Yi-Hui Lee
  • Publication number: 20180068951
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a first gate structure is formed on the substrate, a first spacer is formed around the first gate structure, and an interlayer dielectric (ILD) layer is formed around the first spacer. Next, a first etching process is performed to remove part of the ILD layer for forming a recess, a second etching process is performed to remove part of the first spacer for expanding the recess, and a contact plug is formed in the recess.
    Type: Application
    Filed: October 4, 2016
    Publication date: March 8, 2018
    Inventors: Ching-Wen Hung, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Chih-Sen Huang
  • Patent number: 9899322
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask are used as mask to remove part of the first ILD layer for forming a recess, and a patterned metal layer is formed in the recess, in which the top surface of the patterned metal layer is lower than the top surfaces of the first hard mask and the second hard mask.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: February 20, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Chih-Sen Huang, Ching-Wen Hung, Jia-Rong Wu, Tsung-Hung Chang, Yi-Hui Lee, Yi-Wei Chen
  • Patent number: 9859170
    Abstract: A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each fin structure stretching along a first direction. A plurality of gate structures are formed, and each gate structure stretches along a second direction. Next, a dielectric layer is formed on the gate structures. A first patterned mask layer is formed, wherein the first patterned mask layer has a plurality of first trenches stretching along the second direction. A second patterned mask layer on the first patterned mask layer, wherein the second patterned mask layer comprises a plurality of first patterns stretching along the first direction. Subsequently, the dielectric layer is patterned by using the first patterned mask layer and the second patterned mask layer as a mask to form a plurality of contact vias. The contact holes are filled with a conductive layer.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: January 2, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Wei-Cyuan Lo, Ming-Jui Chen, Chia-Lin Lu, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Yi-Kuan Wu, Chih-Sen Huang, Yi-Wei Chen, Tan-Ya Yin, Chia-Wei Huang, Shu-Ru Wang, Yung-Feng Cheng
  • Patent number: 9831133
    Abstract: A method for manufacturing semiconductor devices having metal gate includes follow steps. A substrate including a plurality of isolation structures is provided. A first nFET device and a second nFET device are formed on the substrate. The first nFET device includes a first gate trench and the second nFET includes a second gate trench. A third bottom barrier layer is formed in the first gate trench and a third p-work function metal layer is formed in the second gate trench, simultaneously. The third bottom barrier layer and the third p-work function metal layer include a same material. An n-work function metal layer is formed in the first gate trench and the second gate trench. The n-work function metal layer in the first gate trench directly contacts the third bottom barrier layer, and the n-work function metal layer in the second gate trench directly contacts the third p-work function metal layer.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: November 28, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chao-Hung Lin, Chih-Kai Hsu, Li-Wei Feng, Shih-Hung Tsai, Chien-Ting Lin, Jyh-Shyang Jenq, Ching-Wen Hung, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Yi-Kuan Wu, Chih-Sen Huang, Yi-Wei Chen
  • Publication number: 20170287843
    Abstract: According to a preferred embodiment of the present invention, a semiconductor device is disclosed. The semiconductor device includes: a substrate having a first region and a second region; a first contact plug on the first region, and a second contact plug on the second region. Preferably, the first contact plug includes a first interfacial layer having a first conductive type and a first work function metal layer having the first conductive type on the first interfacial layer, and the second contact plug includes a second interfacial layer having a second conductive type and a second work function metal layer having the second conductive type on the second interfacial layer.
    Type: Application
    Filed: April 5, 2016
    Publication date: October 5, 2017
    Inventors: Jia-Rong Wu, Ying-Cheng Liu, Ching-Wen Hung, Yi-Hui Lee, Chih-Sen Huang
  • Patent number: 9704785
    Abstract: The invention provides a semiconductor package. The semiconductor package includes a lead frame including a die paddle. A supporting bar connects to the die paddle, extending in an outward direction from the die paddle. At least two power leads are separated from the die paddle and the supporting bar, having first terminals close to the die paddle and second terminals extending outward from the die paddle. A power bar connects to the at least two power leads, having a supporting portion. A molding material encapsulates the lead frame leaving the supporting portion exposed.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: July 11, 2017
    Assignee: MEDIATEK INC.
    Inventors: Tung-Hsien Hsieh, Yi-Hui Lee
  • Publication number: 20170194212
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first fin-shaped structure and a second fin-shaped structure on the substrate; forming a first epitaxial layer on the first fin-shaped structure and a second epitaxial layer on the second fin-shaped structure; and forming a cap layer on the first epitaxial layer and the second epitaxial layer. Preferably, a distance between the first epitaxial layer and the second epitaxial layer is between twice the thickness of the cap layer and four times the thickness of the cap layer.
    Type: Application
    Filed: January 28, 2016
    Publication date: July 6, 2017
    Inventors: Ching-Wen Hung, Ying-Cheng Liu, Jia-Rong Wu, Yi-Hui Lee, Chih-Sen Huang
  • Patent number: 9685337
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of : providing a substrate; forming a first gate structure on the substrate; forming a first contact plug adjacent to the first gate structure; and performing a replacement metal gate (RMG) process to transform the first gate structure into metal gate.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: June 20, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Chih-Sen Huang, Chun-Hsien Lin
  • Publication number: 20170162449
    Abstract: A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each fin structure stretching along a first direction. A plurality of gate structures are formed, and each gate structure stretches along a second direction. Next, a dielectric layer is formed on the gate structures. A first patterned mask layer is formed, wherein the first patterned mask layer has a plurality of first trenches stretching along the second direction. A second patterned mask layer on the first patterned mask layer, wherein the second patterned mask layer comprises a plurality of first patterns stretching along the first direction. Subsequently, the dielectric layer is patterned by using the first patterned mask layer and the second patterned mask layer as a mask to form a plurality of contact vias. The contact holes are filled with a conductive layer.
    Type: Application
    Filed: February 16, 2017
    Publication date: June 8, 2017
    Inventors: Ching-Wen Hung, Wei-Cyuan Lo, Ming-Jui Chen, Chia-Lin Lu, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Yi-Kuan Wu, Chih-Sen Huang, Yi-Wei Chen, Tan-Ya Yin, Chia-Wei Huang, Shu-Ru Wang, Yung-Feng Cheng
  • Patent number: 9660042
    Abstract: A semiconductor device and manufacturing method thereof are provided in the present invention. A second opening is formed corresponding to a gate structure after a step of forming a first opening corresponding to an epitaxial layer. After the step of forming the second opening, a pre-amorphization implantation process is performed to form an amorphous region in the epitaxial layer, and the influence of the process of forming the second opening on the amorphous region may be avoided. The semiconductor device formed by the manufacturing method of the present invention includes a contact structure and an alloy layer. The contact structure is disposed in the second opening for being electrically connected to a metal gate. The alloy layer is disposed on the metal gate and disposed between the metal gate and the contact structure. The alloy layer includes an alloy of the material of the metal gate.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: May 23, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Chih-Sen Huang
  • Publication number: 20170103896
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of : providing a substrate; forming a first gate structure on the substrate; forming a first contact plug adjacent to the first gate structure; and performing a replacement metal gate (RMG) process to transform the first gate structure into metal gate.
    Type: Application
    Filed: August 23, 2016
    Publication date: April 13, 2017
    Inventors: Ching-Wen Hung, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Chih-Sen Huang, Chun-Hsien Lin
  • Publication number: 20170098707
    Abstract: A manufacturing method of a semiconductor structure includes the following steps. An epitaxial region is formed in a semiconductor substrate. A dielectric layer is formed on the epitaxial region, and a contact hole is formed in the dielectric layer. The contact hole exposes a part of the epitaxial region, and an oxide-containing layer is formed on the epitaxial region exposed by the contact hole. A contact structure is formed in the contact hole and on the oxide-containing layer. The oxide-containing layer is located between the contact structure and the epitaxial region. A semiconductor structure includes the semiconductor substrate, at least one epitaxial region, the contact structure, the oxide-containing layer, and a silicide layer. The contact structure is disposed on the epitaxial region. The oxide-containing layer is disposed between the epitaxial region and the contact structure. The silicide layer is disposed between the oxide-containing layer and the contact structure.
    Type: Application
    Filed: November 5, 2015
    Publication date: April 6, 2017
    Inventors: Ching-Wen Hung, Yi-Kuan Wu, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Chih-Sen Huang, Yi-Wei Chen
  • Patent number: 9613969
    Abstract: The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric layer and a plurality of contact plugs. The substrate has a memory region. The fin structures are disposed on the substrate in the memory region, each of which stretches along a first direction. The gate structures are disposed on the fin structures, each of which stretches along a second direction. The dielectric layer is disposed on the gate structures and the fin structures. The contact plugs are disposed in the dielectric layer and electrically connected to a source/drain region in the fin structure. From a top view, the contact plug has a trapezoid shape or a pentagon shape. The present invention further provides a method for forming the same.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: April 4, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Wei-Cyuan Lo, Ming-Jui Chen, Chia-Lin Lu, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Yi-Kuan Wu, Chih-Sen Huang, Yi-Wei Chen, Tan-Ya Yin, Chia-Wei Huang, Shu-Ru Wang, Yung-Feng Cheng
  • Publication number: 20170062282
    Abstract: A method for manufacturing semiconductor devices having metal gate includes follow steps. A substrate including a plurality of isolation structures is provided. A first nFET device and a second nFET device are formed on the substrate. The first nFET device includes a first gate trench and the second nFET includes a second gate trench. A third bottom barrier layer is formed in the first gate trench and a third p-work function metal layer is formed in the second gate trench, simultaneously. The third bottom barrier layer and the third p-work function metal layer include a same material. An n-work function metal layer is formed in the first gate trench and the second gate trench. The n-work function metal layer in the first gate trench directly contacts the third bottom barrier layer, and the n-work function metal layer in the second gate trench directly contacts the third p-work function metal layer.
    Type: Application
    Filed: November 16, 2016
    Publication date: March 2, 2017
    Inventors: Chao-Hung Lin, Chih-Kai Hsu, Li-Wei Feng, Shih-Hung Tsai, Chien-Ting Lin, Jyh-Shyang Jenq, Ching-Wen Hung, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Yi-Kuan Wu, Chih-Sen Huang, Yi-Wei Chen
  • Publication number: 20170047251
    Abstract: A method of manufacturing a semiconductor device includes: providing a semiconductor having active regions; depositing a dielectric layer on the semiconductor; forming a patterned etch mask on the dielectric layer; depositing a further dielectric layer on the dielectric layer and the patterned etch mask; planarizing the further dielectric layer until the patterned etch mask is exposed; and forming a further patterned etch mask having an opening on the further dielectric layer so that portions of the patterned etch mask are exposed from the opening.
    Type: Application
    Filed: August 12, 2015
    Publication date: February 16, 2017
    Inventors: Yi-Hui Lee, Kun-Ju Li, Wei-Cyuan Lo, Ching-Wen Hung, Jia-Rong Wu, Ying-Cheng Liu, Yi-Kuan Wu, Chih-Sen Huang, Yi-Wei Chen
  • Patent number: 9564371
    Abstract: A manufacturing method for forming a semiconductor device includes: first, a substrate is provided, a fin structure is formed on the substrate, and a plurality of gate structures are formed on the fin structure, next, a hard mask layer and a first photoresist layer are formed on the fin structure, an first etching process is then performed on the first photoresist layer, afterwards, a plurality of patterned photoresist layers are formed on the remaining first photoresist layer and the remaining hard mask layer, where each patterned photoresist layer is disposed right above each gate structure, and the width of each patterned photoresist is larger than the width of each gate structure, and the patterned photoresist layer is used as a hard mask to perform an second etching process to form a plurality of second trenches.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: February 7, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Tsung-Hung Chang, Jia-Rong Wu, Ching-Ling Lin, Yi-Hui Lee, Chih-Sen Huang, Yi-Wei Chen
  • Patent number: 9548239
    Abstract: A gate structure is first formed on a substrate and an interlayer dielectric (ILD) layer is formed around the gate structure, a dielectric layer is formed on the ILD layer and the gate structure, an opening is formed in the dielectric layer and the ILD layer, and an organic dielectric layer (ODL) is formed on the dielectric layer and in the opening. After removing part of the ODL, part of the dielectric layer to extend the opening, and then the remaining ODL, a contact plug is formed in the opening.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: January 17, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Feng-Yi Chang, Ching-Wen Hung, Jia-Rong Wu, Yi-Hui Lee, Yi-Kuan Wu, Ying-Cheng Liu, Chih-Sen Huang, Yi-Wei Chen
  • Publication number: 20160379931
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask are used as mask to remove part of the first ILD layer for forming a recess, and a patterned metal layer is formed in the recess, in which the top surface of the patterned metal layer is lower than the top surfaces of the first hard mask and the second hard mask.
    Type: Application
    Filed: September 7, 2016
    Publication date: December 29, 2016
    Inventors: Ching-Ling Lin, Chih-Sen Huang, Ching-Wen Hung, Jia-Rong Wu, Tsung-Hung Chang, Yi-Hui Lee, Yi-Wei Chen