Patents by Inventor Yi-Hung Chiu

Yi-Hung Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210020611
    Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.
    Type: Application
    Filed: October 5, 2020
    Publication date: January 21, 2021
    Inventors: Yi-Da Tsai, Meng-Tse Chen, Sheng-Feng Weng, Sheng-Hsiang Chiu, Wei-Hung Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
  • Patent number: 10878928
    Abstract: Various embodiments of the present application are directed towards a one-time-programmable (OTP) implementation using magnetic junctions. In some embodiments, an array comprises multiple magnetic junctions in multiple columns and multiple rows, and the magnetic junctions comprise a first magnetic junction and a second magnetic junction. The first and second magnetic junctions comprise individual top ferromagnetic elements and individual bottom ferromagnetic elements, and further comprise individual barrier elements between the top and bottom ferromagnetic elements. A first barrier element of the first magnetic junction electrically separates first top and bottom ferromagnetic elements of the first magnetic junction. A second barrier element of the second magnetic junction has undergone breakdown, such that it has defects defining a leakage path between second top and bottom ferromagnetic elements of the second magnetic junction.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry-Hak-Lay Chuang, Tien-Wei Chiang, Wen-Chun You, Yi-Chieh Chiu, Yu-Lin Chen, Jian-Cheng Huang, Chang-Hung Chen
  • Publication number: 20200383335
    Abstract: The present disclosure relates to fungi, a culture filtrate thereof and a polysaccharide and their applications in inducing or priming plant resistance to viruses. Aspects of the present disclosure provides a cultured filtrate, derived from a fungus belonging to the genus Trichosporon, induces strong resistance to various viruses on different plants.
    Type: Application
    Filed: June 5, 2019
    Publication date: December 10, 2020
    Inventors: Hsin-Hung Yeh, Yi-Shu Chiu
  • Publication number: 20200365767
    Abstract: A light-emitting diode structure includes a substrate, a light-generating structure disposed over the substrate, a first electrode adjacent to a first side of the light-generating structure, a second electrode adjacent to a second side of the light-generating structure opposite to the first side, and a tungsten-doped oxide layer disposed in an electrical conduction path between the light-generating structure and one of the first electrode and the second electrode.
    Type: Application
    Filed: October 29, 2019
    Publication date: November 19, 2020
    Inventors: MUNEHISA YANAGISAWA, CHUN-NENG HUANG, CHI-HUNG FENG, HSING-HSUAN LO, TING-WEI CHANG, YI-HSIANG CHIU
  • Publication number: 20200357765
    Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes steps of providing a first wafer including a first substrate and a plurality of first conductors over the first substrate; forming a first interconnect structure penetrating through the first substrate and contacting one of the first conductors; forming a bonding dielectric on the first substrate and the first interconnect structure; bonding a second wafer on the first wafer, wherein the second wafer includes a second substrate, a second ILD layer on a second front surface of the second substrate, and a plurality of second conductors in the second ILD layer, wherein the second ILD layer is in contact with the bonding dielectric; forming a second interconnect structure penetrating through the second substrate and into the second ILD layer and contacting the second conductor and the first interconnect structure.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 12, 2020
    Inventors: PEI-JHEN WU, HSIH-YANG CHIU, CHIANG-LIN SHIH, CHING-HUNG CHANG, YI-JEN LO
  • Patent number: 10811382
    Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes steps of providing a first wafer including a first substrate and a plurality of first conductors over the first substrate; forming a first interconnect structure penetrating through the first substrate and contacting one of the first conductors; forming a bonding dielectric on the first substrate and the first interconnect structure; bonding a second wafer on the first wafer, wherein the second wafer includes a second substrate, a second ILD layer on a second front surface of the second substrate, and a plurality of second conductors in the second ILD layer, wherein the second ILD layer is in contact with the bonding dielectric; forming a second interconnect structure penetrating through the second substrate and into the second ILD layer and contacting the second conductor and the first interconnect structure.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: October 20, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Pei-Jhen Wu, Hsih-Yang Chiu, Chiang-Lin Shih, Ching-Hung Chang, Yi-Jen Lo
  • Patent number: 10797025
    Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Da Tsai, Meng-Tse Chen, Sheng-Feng Weng, Sheng-Hsiang Chiu, Wei-Hung Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
  • Patent number: 10732738
    Abstract: A system module of customizing a screen image based on a non-invasive data-extraction system, and a method thereof are disclosed. The system module is applicable to a machine controller controlling a machine, and sensors are disposed around the machine. In the system module, an image capture device receives an image of an original screen from the machine controller, and transmits the image to the non-invasive data-extraction system for extracting information, and a software control system integrates data measured by the sensors with the information, and combined the integration result with a customized screen image, and an extra control component is embedded in an original operation screen of the machine controller. The customized screen image is shown on the machine controller to display information by more visual manner. Furthermore, the signal receiving device and an HID simulation device can be used to provide a basic function of a KVM switch.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: August 4, 2020
    Assignee: Adlink Technology Inc.
    Inventors: Chua-Hong Ng, Chao-Tung Yang, Wei-Hung Chen, Tsan-Ming Yu, Shih-Hsun Lin, Yang-Chung Tseng, Chih-Fu Hsu, Chien-Hsun Tu, Te-Cheng Chiu, Yi-Wei Lin, Jen-Chi Hsu
  • Publication number: 20200111705
    Abstract: A method includes performing an implantation on a portion of a first layer to form an implanted region, and removing un-implanted portions of the first layer. The implanted region remains after the un-implanted portions of the first layer are removed. An etching is then performed on a second layer underlying the first layer, wherein the implanted region is used as a portion of a first etching mask in the etching. The implanted region is removed. A metal mask is etched using the second layer to form a patterned mask. An inter-layer dielectric is then etched to form a contact opening, wherein the patterned mask is used as a second etching mask.
    Type: Application
    Filed: December 5, 2019
    Publication date: April 9, 2020
    Inventors: Chih-Hung Sun, Han-Ti Hsiaw, Yi-Wei Chiu, Kuan-Cheng Wang, Shin-Yeu Tsai, Jr-Yu Chen, Wen-Cheng Wu
  • Publication number: 20200098440
    Abstract: Various embodiments of the present application are directed towards a one-time-programmable (OTP) implementation using magnetic junctions. In some embodiments, an array comprises multiple magnetic junctions in multiple columns and multiple rows, and the magnetic junctions comprise a first magnetic junction and a second magnetic junction. The first and second magnetic junctions comprise individual top ferromagnetic elements and individual bottom ferromagnetic elements, and further comprise individual barrier elements between the top and bottom ferromagnetic elements. A first barrier element of the first magnetic junction electrically separates first top and bottom ferromagnetic elements of the first magnetic junction. A second barrier element of the second magnetic junction has undergone breakdown, such that it has defects defining a leakage path between second top and bottom ferromagnetic elements of the second magnetic junction.
    Type: Application
    Filed: May 13, 2019
    Publication date: March 26, 2020
    Inventors: Harry-Hak-Lay Chuang, Tien-Wei Chiang, Wen-Chun You, Yi-Chieh Chiu, Yu-Lin Chen, Jian-Cheng Huang, Chang-Hung Chen
  • Patent number: 10510593
    Abstract: A method includes performing an implantation on a portion of a first layer to form an implanted region, and removing un-implanted portions of the first layer. The implanted region remains after the un-implanted portions of the first layer are removed. An etching is then performed on a second layer underlying the first layer, wherein the implanted region is used as a portion of a first etching mask in the etching. The implanted region is removed. A metal mask is etched using the second layer to form a patterned mask. An inter-layer dielectric is then etched to form a contact opening, wherein the patterned mask is used as a second etching mask.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hung Sun, Han-Ti Hsiaw, Yi-Wei Chiu, Kuan-Cheng Wang, Shin-Yeu Tsai, Jr-Yu Chen, Wen-Cheng Wu
  • Publication number: 20190353170
    Abstract: A method for controlling a fan in a fan start-up stage including a first time period and a second time period comprises the following steps of: during the first time period, continuously providing a first driving signal to drive the fan; and during the second time period, continuously providing a second driving signal to drive the fan; wherein, during the first time period the signal value (driving energy) of the first driving signal gradually decreases until being equal to the signal value of the second driving signal, and the signal value of the first driving signal is initially greater than the signal value of the second driving signal. A fan is also disclosed.
    Type: Application
    Filed: July 29, 2019
    Publication date: November 21, 2019
    Inventors: Yi-Fan LIN, Chung-Hung TANG, Cheng-Chieh LIU, Chun-Lung CHIU
  • Patent number: 10420975
    Abstract: The present invention provides an active and passive exercise training equipment comprising a swinging device, a supporting device, and a front supporting device. The swinging device comprises a seat cushion with moving function for a user to sit. The supporting device comprises a telescopic rack and a top rack for the user to grip. The top rack is set on the telescopic rack for being located at different heights. The front supporting device comprises a front telescopic rack and a front grip for the user to bend forward to grip. The grip is set on the front telescopic rack for being located at different horizontal distances and vertical heights. The height and the distance can be adjusted according to the stature or requirement of the user so that the user can train his muscular strength efficiently and also make his body to achieve a relaxed state.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: September 24, 2019
    Assignee: CHENG SHIU UNIVERSITY
    Inventors: Pin-Hung Chuang, Yi-Ta Chuang, Yu-Hsien Chiu
  • Patent number: 9224862
    Abstract: A high voltage semiconductor device is provided. The device includes a semiconductor substrate having a high voltage well with a first conductivity type therein. A gate structure is disposed on the semiconductor substrate of the high voltage well. A source doped region and a drain doped region are in the high voltage well on both sides of the gate structure, respectively. A lightly doped region with the first conductivity type is between the source and drain doped regions and relatively near to the source doped region. The disclosure also presents a method for fabricating a high voltage semiconductor device.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: December 29, 2015
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Wei-Chun Chou, Yi-Hung Chiu, Chu-Feng Chen, Cheng-Yi Hsieh, Chung-Ren Lao
  • Patent number: 9083080
    Abstract: An antenna structure is provided, including a first radiator, a second radiator, a second coupling portion and a switch Circuit. The first radiator includes a feed portion and a first radiator body. The second radiator includes a first coupling portion, a second radiator body and a ground portion. The first coupling portion is connected to a first end portion of the second radiator body. The ground portion is connected to the second radiator body. At least a portion of the first radiator body is located between the first coupling portion and the second coupling portion. When the antenna structure is in a first mode, the switch circuit forms an electric path between the second radiator and the second coupling portion, and when the antenna structure is in a second mode, the switch circuit removes the electric path between the second radiator and the second coupling portion.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: July 14, 2015
    Assignee: WISTRON NEWEB CORP.
    Inventors: Chung-Hung Chen, Yi-Hung Chiu, Chia-Hao Chang, Chih-Sen Hsieh
  • Publication number: 20150054071
    Abstract: A high voltage semiconductor device is provided. The device includes a semiconductor substrate having a high voltage well with a first conductivity type therein. A gate structure is disposed on the semiconductor substrate of the high voltage well. A source doped region and a drain doped region are in the high voltage well on both sides of the gate structure, respectively. A lightly doped region with the first conductivity type is between the source and drain doped regions and relatively near to the source doped region. The disclosure also presents a method for fabricating a high voltage semiconductor device.
    Type: Application
    Filed: August 26, 2014
    Publication date: February 26, 2015
    Inventors: Wei-Chun CHOU, Yi-Hung CHIU, Chu-Feng CHEN, Cheng-Yi HSIEH, Chung-Ren LAO
  • Patent number: 8847332
    Abstract: A high voltage semiconductor device is provided. The device includes a semiconductor substrate having a high voltage well with a first conductivity type therein. A gate structure is disposed on the semiconductor substrate of the high voltage well. A source doped region and a drain doped region are in the high voltage well on both sides of the gate structure, respectively. A lightly doped region with the first conductivity type is between the source and drain doped regions and relatively near to the source doped region. The disclosure also presents a method for fabricating a high voltage semiconductor device.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: September 30, 2014
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Wei-Chun Chou, Yi-Hung Chiu, Chu-Feng Chen, Cheng-Yi Hsieh, Chung-Ren Lao
  • Publication number: 20140104134
    Abstract: An antenna structure is provided, including a first radiator, a second radiator, a second coupling portion and a switch Circuit. The first radiator includes a feed portion and a first radiator body. The second radiator includes a first coupling portion, a second radiator body and a ground portion. The first coupling portion is connected to a first end portion of the second radiator body. The ground portion is connected to the second radiator body. At least a portion of the first radiator body is located between the first coupling portion and the second coupling portion. When the antenna structure is in a first mode, the switch circuit forms an electric path between the second radiator and the second coupling portion, and when the antenna structure is in a second mode, the switch circuit removes the electric path between the second radiator and the second coupling portion.
    Type: Application
    Filed: July 30, 2013
    Publication date: April 17, 2014
    Applicant: Wistron NeWeb Corp.
    Inventors: Chung-Hung CHEN, Yi-Hung CHIU, Chia-Hao CHANG, Chih-Sen HSIEH
  • Publication number: 20120267715
    Abstract: A high voltage semiconductor device is provided. The device includes a semiconductor substrate having a high voltage well with a first conductivity type therein. A gate structure is disposed on the semiconductor substrate of the high voltage well. A source doped region and a drain doped region are in the high voltage well on both sides of the gate structure, respectively. A lightly doped region with the first conductivity type is between the source and drain doped regions and relatively near to the source doped region. The disclosure also presents a method for fabricating a high voltage semiconductor device.
    Type: Application
    Filed: April 20, 2011
    Publication date: October 25, 2012
    Inventors: Wei-Chun CHOU, Yi-Hung CHIU, Chu-Feng CHEN, Cheng-Yi HSIEH, Chung-Ren LAO
  • Patent number: 7911390
    Abstract: An antenna structure includes a radiation element, a grounding element, a short point, and a feeding point. The radiation element includes a first radiator and a second radiator. The second radiator partially surrounds the first radiator and there is a predetermined distance included between the first radiator and the second radiator for matching impedance. The short point is coupled between the second radiator and the grounding element. The feeding point is coupled between a joint point of the first radiator and the second radiator and the grounding element.
    Type: Grant
    Filed: April 9, 2008
    Date of Patent: March 22, 2011
    Assignee: Wistron NeWeb Corporation
    Inventor: Yi-Hung Chiu